arm/ti/ti_adc.c

156 	ADC_WRITE4(sc, ADC_CTRL, ADC_READ4(sc, ADC_CTRL) & ~ADC_CTRL_ENABLE);
163 	ADC_WRITE4(sc, ADC_IRQSTATUS, ADC_READ4(sc, ADC_IRQSTATUS));
166 	count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK;
168 		data = ADC_READ4(sc, ADC_FIFO0DATA);
169 		count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK;
172 	count = ADC_READ4(sc, ADC_FIFO1COUNT) & ADC_FIFO_COUNT_MSK;
174 		data = ADC_READ4(sc, ADC_FIFO1DATA);
175 		count = ADC_READ4(sc, ADC_FIFO1COUNT) & ADC_FIFO_COUNT_MSK;
201 		if (enabled != ADC_READ4(sc, ADC_STEPENABLE))
219 	val = ADC_READ4(sc, reg);
267 	reg = (int)ADC_READ4(sc, ADC_CLKDIV) + 1;
341 	reg = (int)ADC_READ4(sc, input->stepdelay) & ADC_STEP_OPEN_DELAY;
399 	count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK;
401 		data = ADC_READ4(sc, ADC_FIFO0DATA);
408 		count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK;
437 	count = ADC_READ4(sc, ADC_FIFO1COUNT) & ADC_FIFO_COUNT_MSK;
443 		data[i++] = ADC_READ4(sc, ADC_FIFO1DATA) & ADC_FIFO_DATA_MSK;
444 		count = ADC_READ4(sc, ADC_FIFO1COUNT) & ADC_FIFO_COUNT_MSK;
510 	rawstatus = ADC_READ4(sc, ADC_IRQSTATUS_RAW);
511 	status = ADC_READ4(sc, ADC_IRQSTATUS);
663 	val = ADC_READ4(sc, ADC_IDLECONFIG);
848 	rev = ADC_READ4(sc, ti_sysc_get_rev_address_offset_host(device_get_parent(dev)));
858 	reg = ADC_READ4(sc, ADC_CTRL);