Lines Matching refs:cpsw_write_4
374 #define cpsw_write_4(_sc, _reg, _val) \
386 cpsw_write_4(sc, slot->bd_offset, cpsw_cpdma_bd_paddr(sc, next_slot))
392 cpsw_write_4(sc, (queue)->hdp_offset, cpsw_cpdma_bd_paddr(sc, slot))
397 cpsw_write_4(sc, (queue)->hdp_offset + CP_OFFSET, (val))
409 cpsw_write_4(sc, reg, v);
556 cpsw_write_4(sc, CPSW_WR_SOFT_RESET, 1);
562 cpsw_write_4(sc, CPSW_WR_C_RX_THRESH_EN(i), 0x00);
563 cpsw_write_4(sc, CPSW_WR_C_TX_EN(i), 0x00);
564 cpsw_write_4(sc, CPSW_WR_C_RX_EN(i), 0x00);
565 cpsw_write_4(sc, CPSW_WR_C_MISC_EN(i), 0x00);
569 cpsw_write_4(sc, CPSW_SS_SOFT_RESET, 1);
576 cpsw_write_4(sc, CPSW_SL_SOFT_RESET(i), 1);
582 cpsw_write_4(sc, CPSW_CPDMA_SOFT_RESET, 1);
587 cpsw_write_4(sc, CPSW_CPDMA_TX_CONTROL, 0);
588 cpsw_write_4(sc, CPSW_CPDMA_RX_CONTROL, 0);
592 cpsw_write_4(sc, CPSW_CPDMA_TX_HDP(i), 0);
593 cpsw_write_4(sc, CPSW_CPDMA_RX_HDP(i), 0);
594 cpsw_write_4(sc, CPSW_CPDMA_TX_CP(i), 0);
595 cpsw_write_4(sc, CPSW_CPDMA_RX_CP(i), 0);
599 cpsw_write_4(sc, CPSW_CPDMA_RX_INTMASK_CLEAR, 0xFFFFFFFF);
600 cpsw_write_4(sc, CPSW_CPDMA_TX_INTMASK_CLEAR, 0xFFFFFFFF);
612 cpsw_write_4(sc, CPSW_WR_INT_CONTROL, reg);
615 cpsw_write_4(sc, CPSW_ALE_CONTROL, CPSW_ALE_CTL_CLEAR_TBL);
621 cpsw_write_4(sc, CPSW_ALE_CONTROL, reg);
624 cpsw_write_4(sc, CPSW_PORT_P0_CPDMA_TX_PRI_MAP, 0x76543210);
625 cpsw_write_4(sc, CPSW_PORT_P0_CPDMA_RX_CH_MAP, 0);
628 cpsw_write_4(sc, CPSW_ALE_PORTCTL(0),
631 cpsw_write_4(sc, CPSW_SS_PTYPE, 0);
634 cpsw_write_4(sc, CPSW_SS_STAT_PORT_EN, 7);
637 cpsw_write_4(sc, CPSW_SS_FLOW_CONTROL, 0);
640 cpsw_write_4(sc, CPSW_CPDMA_RX_BUFFER_OFFSET, 2);
643 cpsw_write_4(sc, CPSW_CPDMA_RX_PENDTHRESH(0), 0);
644 cpsw_write_4(sc, CPSW_CPDMA_RX_FREEBUFFER(0), 0);
647 cpsw_write_4(sc, CPSW_CPDMA_TX_CONTROL, 1);
648 cpsw_write_4(sc, CPSW_CPDMA_RX_CONTROL, 1);
651 cpsw_write_4(sc, CPSW_WR_C_RX_THRESH_EN(0), 0xFF);
652 cpsw_write_4(sc, CPSW_WR_C_RX_EN(0), 0xFF);
653 cpsw_write_4(sc, CPSW_WR_C_TX_EN(0), 0xFF);
654 cpsw_write_4(sc, CPSW_WR_C_MISC_EN(0), 0x1F);
657 cpsw_write_4(sc, CPSW_CPDMA_DMA_INTMASK_SET, 3);
660 cpsw_write_4(sc, CPSW_CPDMA_RX_INTMASK_SET,
662 cpsw_write_4(sc, CPSW_CPDMA_TX_INTMASK_SET, 1);
666 cpsw_write_4(sc, MDIOCONTROL, MDIOCTL_ENABLE | MDIOCTL_FAULTENB | 0xff);
679 cpsw_write_4(sc, CPSW_CPDMA_RX_FREEBUFFER(0), sc->rx.active_queue_len);
680 cpsw_write_4(sc, CPSW_CPDMA_RX_PENDTHRESH(0), CPSW_TXFRAGS);
1094 cpsw_write_4(sc->swsc, sc->physel,
1186 cpsw_write_4(sc->swsc, CPSW_SL_RX_PRI_MAP(sc->unit), 0x76543210);
1187 cpsw_write_4(sc->swsc, CPSW_PORT_P_TX_PRI_MAP(sc->unit + 1),
1189 cpsw_write_4(sc->swsc, CPSW_SL_RX_MAXLEN(sc->unit), 0x5f2);
1195 cpsw_write_4(sc->swsc, CPSW_SL_MACCONTROL(sc->unit), reg);
1198 cpsw_write_4(sc->swsc, CPSW_ALE_PORTCTL(sc->unit + 1),
1204 cpsw_write_4(sc->swsc, CPSW_PORT_P_VLAN(sc->unit + 1),
1255 cpsw_write_4(sc, CPSW_CPDMA_RX_TEARDOWN, 0);
1278 cpsw_write_4(sc, CPSW_CPDMA_TX_TEARDOWN, 0);
1325 cpsw_write_4(sc->swsc, CPSW_SL_MACCONTROL(sc->unit), reg);
1394 cpsw_write_4(sc->swsc, CPSW_ALE_CONTROL, reg);
1508 cpsw_write_4(sc->swsc, sc->phyaccess, cmd);
1538 cpsw_write_4(sc->swsc, sc->phyaccess, cmd);
1577 cpsw_write_4(sc->swsc, reg, mac_control);
1601 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, 1);
1817 cpsw_write_4(sc, CPSW_CPDMA_RX_FREEBUFFER(0), added);
1848 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, 2);
2089 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, 0);
2178 cpsw_write_4(sc, CPSW_CPDMA_DMA_INTMASK_CLEAR, intstat);
2197 cpsw_write_4(sc, MDIOLINKINTMASKED,
2204 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, 3);
2324 cpsw_write_4(sc, CPSW_ALE_TBLCTL, idx & 1023);
2333 cpsw_write_4(sc, CPSW_ALE_TBLW0, ale_entry[0]);
2334 cpsw_write_4(sc, CPSW_ALE_TBLW1, ale_entry[1]);
2335 cpsw_write_4(sc, CPSW_ALE_TBLW2, ale_entry[2]);
2336 cpsw_write_4(sc, CPSW_ALE_TBLCTL, 1 << 31 | (idx & 1023));
2492 cpsw_write_4(sc->swsc, CPSW_PORT_P_SA_HI(sc->unit + 1),
2494 cpsw_write_4(sc->swsc, CPSW_PORT_P_SA_LO(sc->unit + 1),
2587 cpsw_write_4(sc, CPSW_STATS_OFFSET + cpsw_stat_sysctls[i].reg,
2636 cpsw_write_4(sc, CPSW_WR_INT_CONTROL, ctrl);
2637 cpsw_write_4(sc, CPSW_WR_C_RX_IMAX(0), 0);
2638 cpsw_write_4(sc, CPSW_WR_C_TX_IMAX(0), 0);
2657 cpsw_write_4(sc, CPSW_WR_C_RX_IMAX(0), intr_per_ms);
2658 cpsw_write_4(sc, CPSW_WR_C_TX_IMAX(0), intr_per_ms);
2660 cpsw_write_4(sc, CPSW_WR_INT_CONTROL, ctrl);
2870 cpsw_write_4(sc, CPSW_PORT_P_VLAN(p->es_port),
2883 cpsw_write_4(sc, CPSW_ALE_PORTCTL(p->es_port), reg);