Lines Matching defs:timer
96 } timer[VHPET_NUM_TIMERS];
113 cap &= ~HPET_CAP_COUNT_SIZE; /* 32-bit timer */
133 if ((vhpet->timer[n].cap_config & msi_enable) == msi_enable)
143 * If the timer is configured to use MSI then treat it as if the
144 * timer is not connected to the ioapic.
149 return ((vhpet->timer[n].cap_config & HPET_TCNF_INT_ROUTE) >> 9);
185 KASSERT(pin != 0, ("vhpet timer %d irq incorrectly routed", n));
195 return ((vhpet->timer[n].cap_config & HPET_TCNF_TYPE) != 0);
202 return ((vhpet->timer[n].cap_config & HPET_TCNF_INT_ENB) != 0);
210 "timer %d is using MSI", n));
212 if ((vhpet->timer[n].cap_config & HPET_TCNF_INT_TYPE) == 0)
223 /* If interrupts are not enabled for this timer then just return. */
236 lapic_intr_msi(vhpet->vm, vhpet->timer[n].msireg >> 32,
237 vhpet->timer[n].msireg & 0xffffffff);
260 KASSERT(vhpet->timer[n].comprate != 0, ("hpet t%d is not periodic", n));
262 compval = vhpet->timer[n].compval;
263 comprate = vhpet->timer[n].comprate;
278 vhpet->timer[n].compval = compnext;
294 callout = &vhpet->timer[n].callout;
324 callout_stop(&vhpet->timer[n].callout);
328 * had a chance to execute yet then trigger the timer interrupt
329 * here. Failing to do so will result in a missed timer interrupt
333 if (vhpet->timer[n].callout_sbt < now) {
335 "stopping timer", n);
345 if (vhpet->timer[n].comprate != 0)
356 delta = (vhpet->timer[n].compval - counter) * vhpet->freq_sbt;
358 vhpet->timer[n].callout_sbt = now + delta;
359 callout_reset_sbt(&vhpet->timer[n].callout, vhpet->timer[n].callout_sbt,
360 precision, vhpet_handler, &vhpet->timer[n].arg, C_ABSOLUTE);
409 panic("vhpet timer %d isr should not be asserted", n);
412 oldval = vhpet->timer[n].cap_config;
422 vhpet->timer[n].cap_config = newval;
430 allowed_irqs = vhpet->timer[n].cap_config >> 32;
436 vhpet->timer[n].cap_config &= ~HPET_TCNF_INT_ROUTE;
440 vhpet->timer[n].comprate = 0;
443 * If the timer's ISR bit is set then clear it in the following cases:
448 * This is to ensure that this timer's level triggered interrupt does
452 KASSERT(old_pin != 0, ("timer %d isr asserted to ioapic pin %d",
576 old_compval = vhpet->timer[i].compval;
577 old_comprate = vhpet->timer[i].comprate;
585 val64 = vhpet->timer[i].comprate;
587 vhpet->timer[i].comprate = val64;
588 if ((vhpet->timer[i].cap_config &
590 vhpet->timer[i].compval = val64;
593 KASSERT(vhpet->timer[i].comprate == 0,
594 ("vhpet one-shot timer %d has invalid "
595 "rate %u", i, vhpet->timer[i].comprate));
596 val64 = vhpet->timer[i].compval;
598 vhpet->timer[i].compval = val64;
600 vhpet->timer[i].cap_config &= ~HPET_TCNF_VAL_SET;
602 if (vhpet->timer[i].compval != old_compval ||
603 vhpet->timer[i].comprate != old_comprate) {
615 update_register(&vhpet->timer[i].msireg, data, mask);
676 data = vhpet->timer[i].cap_config;
682 data = vhpet->timer[i].compval;
688 data = vhpet->timer[i].msireg;
731 * Initialize HPET timer hardware state.
734 vhpet->timer[i].cap_config = allowed_irqs << 32;
735 vhpet->timer[i].cap_config |= HPET_TCAP_PER_INT;
736 vhpet->timer[i].cap_config |= HPET_TCAP_FSB_INT_DEL;
738 vhpet->timer[i].compval = 0xffffffff;
739 callout_init(&vhpet->timer[i].callout, 1);
741 arg = &vhpet->timer[i].arg;
755 callout_drain(&vhpet->timer[i].callout);
790 for (i = 0; i < nitems(vhpet->timer); i++) {
791 SNAPSHOT_VAR_OR_LEAVE(vhpet->timer[i].cap_config,
793 SNAPSHOT_VAR_OR_LEAVE(vhpet->timer[i].msireg, meta, ret, done);
794 SNAPSHOT_VAR_OR_LEAVE(vhpet->timer[i].compval, meta, ret, done);
795 SNAPSHOT_VAR_OR_LEAVE(vhpet->timer[i].comprate, meta, ret, done);
796 SNAPSHOT_VAR_OR_LEAVE(vhpet->timer[i].callout_sbt,