Lines Matching refs:RISCV
20 .for arch in AArch64 ARM BPF Mips PowerPC RISCV X86
1262 SRCS_MIN+= Target/RISCV/AsmParser/RISCVAsmParser.cpp
1263 SRCS_MIN+= Target/RISCV/Disassembler/RISCVDisassembler.cpp
1264 SRCS_MIN+= Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
1265 SRCS_MIN+= Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
1266 SRCS_MIN+= Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
1267 SRCS_MIN+= Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
1268 SRCS_MIN+= Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.cpp
1269 SRCS_MIN+= Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
1270 SRCS_MIN+= Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp
1271 SRCS_MIN+= Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
1272 SRCS_MIN+= Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
1273 SRCS_MIN+= Target/RISCV/RISCVAsmPrinter.cpp
1274 SRCS_MIN+= Target/RISCV/RISCVCallLowering.cpp
1275 SRCS_MIN+= Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
1276 SRCS_MIN+= Target/RISCV/RISCVExpandPseudoInsts.cpp
1277 SRCS_MIN+= Target/RISCV/RISCVFrameLowering.cpp
1278 SRCS_MIN+= Target/RISCV/RISCVInstrInfo.cpp
1279 SRCS_MIN+= Target/RISCV/RISCVInstructionSelector.cpp
1280 SRCS_MIN+= Target/RISCV/RISCVISelDAGToDAG.cpp
1281 SRCS_MIN+= Target/RISCV/RISCVISelLowering.cpp
1282 SRCS_MIN+= Target/RISCV/RISCVLegalizerInfo.cpp
1283 SRCS_MIN+= Target/RISCV/RISCVMCInstLower.cpp
1284 SRCS_MIN+= Target/RISCV/RISCVMergeBaseOffset.cpp
1285 SRCS_MIN+= Target/RISCV/RISCVRegisterBankInfo.cpp
1286 SRCS_MIN+= Target/RISCV/RISCVRegisterInfo.cpp
1287 SRCS_MIN+= Target/RISCV/RISCVSubtarget.cpp
1288 SRCS_MIN+= Target/RISCV/RISCVTargetMachine.cpp
1289 SRCS_MIN+= Target/RISCV/RISCVTargetObjectFile.cpp
1290 SRCS_MIN+= Target/RISCV/RISCVTargetTransformInfo.cpp
1291 SRCS_MIN+= Target/RISCV/TargetInfo/RISCVTargetInfo.cpp
1292 SRCS_MIN+= Target/RISCV/Utils/RISCVBaseInfo.cpp
1293 SRCS_MIN+= Target/RISCV/Utils/RISCVMatInt.cpp
1706 Mips/mips NVPTX/nvvm PowerPC/ppc R600/r600 RISCV/riscv S390/s390 \
1747 AArch64/AArch64 ARM/ARM BPF/BPF Mips/Mips PowerPC/PPC RISCV/RISCV \