Lines Matching defs:owner_sr_opcode
94 uint8_t owner_sr_opcode;
107 return (!!(tcqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^
124 cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK);
161 switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) {
260 is_send = cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK;
261 is_error = (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
324 switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) {
505 if (cq->cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK) {
506 switch (cq->cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) {
526 switch (cq->cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) {
549 int is_send = cq->cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK;
553 switch (cq->cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) {
566 switch (cq->cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) {
600 switch (cq->cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) {
742 !(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK)) {
746 if (srq && !(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK))
752 owner_bit = dest->owner_sr_opcode & MLX4_CQE_OWNER_MASK;
754 dest->owner_sr_opcode = owner_bit |
755 (dest->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK);
797 while ((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) != MLX4_CQE_OPCODE_RESIZE) {
798 cqe->owner_sr_opcode = (cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK) |