Lines Matching refs:ATF_TP_ADD_TC
208 ATF_TP_ADD_TC(tp, lwp_create_works);
209 ATF_TP_ADD_TC(tp, lwp_create_generic_fail_no_uc_cpu);
211 ATF_TP_ADD_TC(tp, lwp_create_alpha_fail_pslset);
212 ATF_TP_ADD_TC(tp, lwp_create_alpha_fail_pslclr);
215 ATF_TP_ADD_TC(tp, lwp_create_amd64_fail_untouchable_rflags);
216 ATF_TP_ADD_TC(tp, lwp_create_amd64_fail_pc_too_high);
219 ATF_TP_ADD_TC(tp, lwp_create_arm_fail_invalid_mode);
222 ATF_TP_ADD_TC(tp, lwp_create_hppa_fail_invalid_1);
223 ATF_TP_ADD_TC(tp, lwp_create_hppa_fail_invalid_0);
226 ATF_TP_ADD_TC(tp, lwp_create_i386_fail_untouchable_eflags);
227 ATF_TP_ADD_TC(tp, lwp_create_i386_fail_priv_escalation);
230 ATF_TP_ADD_TC(tp, lwp_create_m68k_fail_invalid_ps_bits);
233 ATF_TP_ADD_TC(tp, lwp_create_sh3_fail_modify_userstatic);
236 ATF_TP_ADD_TC(tp, lwp_create_sparc_fail_pc_odd);
237 ATF_TP_ADD_TC(tp, lwp_create_sparc_fail_npc_odd);
238 ATF_TP_ADD_TC(tp, lwp_create_sparc_fail_pc_null);
239 ATF_TP_ADD_TC(tp, lwp_create_sparc_fail_npc_null);
242 ATF_TP_ADD_TC(tp, lwp_create_vax_fail_psl_0);
243 ATF_TP_ADD_TC(tp, lwp_create_vax_fail_psl_1);
244 ATF_TP_ADD_TC(tp, lwp_create_vax_fail_psl_cm);