Lines Matching defs:RegisterClasses
135 const auto &RegisterClasses = Bank.getRegClasses();
136 if (!RegisterClasses.empty()) {
139 assert(RegisterClasses.size() <= 0xffff &&
146 for (const auto &RC : RegisterClasses)
1042 const auto &RegisterClasses = RegBank.getRegClasses();
1050 for (const auto &RC : RegisterClasses) {
1087 for (const auto &RC : RegisterClasses) {
1125 << RegisterClasses.size() << ", " << TargetName << "RegUnitRoots, "
1190 const auto &RegisterClasses = RegBank.getRegClasses();
1192 if (!RegisterClasses.empty()) {
1193 OS << "namespace " << RegisterClasses.front().Namespace
1196 for (const auto &RC : RegisterClasses) {
1202 OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n\n";
1226 const auto &RegisterClasses = RegBank.getRegClasses();
1233 for (const auto &RC : RegisterClasses) {
1246 for (const auto &RC : RegisterClasses) {
1279 if (!RegisterClasses.empty()) {
1290 for (const auto &RC : RegisterClasses) {
1329 SmallVector<IdxList, 8> SuperRegIdxLists(RegisterClasses.size());
1331 BitVector MaskBV(RegisterClasses.size());
1333 for (const auto &RC : RegisterClasses) {
1361 for (const auto &RC : RegisterClasses) {
1376 for (const auto &RC : RegisterClasses) {
1408 OS << "\nnamespace " << RegisterClasses.front().Namespace
1411 for (const auto &RC : RegisterClasses) {
1434 OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n";
1438 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
1439 for (const auto &RC : RegisterClasses)
1477 if (RegisterClasses.size() < UINT8_MAX)
1479 else if (RegisterClasses.size() < UINT16_MAX)
1483 OS << RegisterClasses.size() << "][" << SubRegIndicesSize << "] = {\n";
1484 for (const auto &RC : RegisterClasses) {
1522 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() << ",\n"
1529 << "MCRegisterClasses, " << RegisterClasses.size() << ",\n"