Lines Matching defs:v16i16
413 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence
414 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence
415 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence
416 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence
439 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split.
440 { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split.
443 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split.
444 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split.
479 { ISD::SHL, MVT::v16i16, 1 }, // vpsllvw
480 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw
481 { ISD::SRA, MVT::v16i16, 1 }, // vpsravw
494 { ISD::SHL, MVT::v16i16, 1 }, // psllw.
495 { ISD::SRL, MVT::v16i16, 1 }, // psrlw.
496 { ISD::SRA, MVT::v16i16, 1 }, // psraw.
620 if (ISD == ISD::SHL && LT.second == MVT::v16i16 &&
623 // On AVX2, a packed v16i16 shift left by a constant build_vector
652 { ISD::SHL, MVT::v16i16, 2+2 },
653 { ISD::SRL, MVT::v16i16, 4+2 },
654 { ISD::SRA, MVT::v16i16, 4+2 },
679 { ISD::SHL, MVT::v16i16, 2+2 }, // 2*psllw + split.
683 { ISD::SRL, MVT::v16i16, 2+2 }, // 2*psrlw + split.
687 { ISD::SRA, MVT::v16i16, 2+2 }, // 2*psraw + split.
712 ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX()))
719 { ISD::SHL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence.
724 { ISD::SRL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence.
729 { ISD::SRA, MVT::v16i16, 10 }, // extend/vpsravd/pack sequence.
736 { ISD::SUB, MVT::v16i16, 1 }, // psubw
737 { ISD::ADD, MVT::v16i16, 1 }, // paddw
745 { ISD::MUL, MVT::v16i16, 1 }, // pmullw
773 { ISD::MUL, MVT::v16i16, 4 },
777 { ISD::SUB, MVT::v16i16, 4 },
778 { ISD::ADD, MVT::v16i16, 4 },
835 { ISD::SHL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split.
842 { ISD::SRL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split.
849 { ISD::SRA, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split.
1101 {TTI::SK_Reverse, MVT::v16i16, 2}, // vpermw
1105 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 2}, // vpermw
1109 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 2}, // vpermt2w
1176 {TTI::SK_Broadcast, MVT::v16i16, 1}, // vpbroadcastw
1183 {TTI::SK_Reverse, MVT::v16i16, 2}, // vperm2i128 + pshufb
1186 {TTI::SK_Select, MVT::v16i16, 1}, // vpblendvb
1193 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vperm2i128 + 2*vpshufb
1202 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 7}, // 2*vperm2i128 + 4*vpshufb
1217 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vextractf128 + 2*vpperm
1222 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 9}, // 2*vextractf128 + 6*vpperm
1239 {TTI::SK_Broadcast, MVT::v16i16, 3}, // vpshuflw + vpshufd + vinsertf128
1246 {TTI::SK_Reverse, MVT::v16i16, 4}, // vextractf128 + 2*pshufb
1255 {TTI::SK_Select, MVT::v16i16, 3}, // vpand + vpandn + vpor
1262 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 8}, // vextractf128 + 4*pshufb
1271 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 15}, // 2*vextractf128 + 8*pshufb
1397 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 },
1410 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 },
1416 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, // widen to zmm
1424 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, // widen to zmm
1459 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 3 }, // sext+vpslld+vptestmd
1468 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 2 },
1475 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, // extend to v16i32
1497 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 3 },
1498 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 },
1518 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 },
1519 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 },
1535 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 },
1544 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 },
1553 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 3 },
1559 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 3 },
1572 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 },
1583 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 },
1586 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 },
1594 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, // vpsllw+vptestmw
1628 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 8 }, // split+2*v8i16
1655 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 10 },
1656 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 12 },
1709 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 },
1710 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 1 },
1711 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 },
1712 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 },
1719 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 3 },
1720 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 3 },
1745 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 4 },
1746 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 },
1747 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 },
1748 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 4 },
1758 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 4 },
1762 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 4 },
1846 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 },
1847 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 },
1854 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 4 },
1855 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 4 },
1869 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 6 },
1937 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 },
1938 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 },
1947 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 6 },
1948 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 8 },
1963 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 },
1971 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 10 },
2145 { ISD::SETCC, MVT::v16i16, 1 },
2150 { ISD::SELECT, MVT::v16i16, 1 }, // pblendvb
2160 { ISD::SETCC, MVT::v16i16, 4 },
2167 { ISD::SELECT, MVT::v16i16, 3 }, // vandps + vandnps + vorps
2265 { ISD::CTLZ, MVT::v16i16, 4 },
2343 { ISD::BITREVERSE, MVT::v16i16, 4 },
2357 { ISD::BITREVERSE, MVT::v16i16, 5 },
2361 { ISD::BSWAP, MVT::v16i16, 1 },
2364 { ISD::CTLZ, MVT::v16i16, 14 },
2368 { ISD::CTPOP, MVT::v16i16, 9 },
2372 { ISD::CTTZ, MVT::v16i16, 12 },
2374 { ISD::SADDSAT, MVT::v16i16, 1 },
2376 { ISD::SSUBSAT, MVT::v16i16, 1 },
2378 { ISD::UADDSAT, MVT::v16i16, 1 },
2381 { ISD::USUBSAT, MVT::v16i16, 1 },
2394 { ISD::BITREVERSE, MVT::v16i16, 12 }, // 2 x 128-bit Op + extract/insert
2398 { ISD::BSWAP, MVT::v16i16, 4 },
2401 { ISD::CTLZ, MVT::v16i16, 30 }, // 2 x 128-bit Op + extract/insert
2405 { ISD::CTPOP, MVT::v16i16, 20 }, // 2 x 128-bit Op + extract/insert
2409 { ISD::CTTZ, MVT::v16i16, 26 }, // 2 x 128-bit Op + extract/insert
2411 { ISD::SADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert
2413 { ISD::SSUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert
2415 { ISD::UADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert
2418 { ISD::USUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert
2741 { ISD::ROTL, MVT::v16i16, 4 },
2749 { ISD::ROTR, MVT::v16i16, 6 },
3157 { ISD::ADD, MVT::v16i16, 5 },
3229 { ISD::AND, MVT::v16i16, 2 }, // vpmovmskb + cmp
3231 { ISD::OR, MVT::v16i16, 2 }, // vpmovmskb + cmp
3238 { ISD::AND, MVT::v16i16, 4 }, // vextractf128 + vpand + vpmovmskb + cmp
3242 { ISD::OR, MVT::v16i16, 4 }, // vextractf128 + vpor + vpmovmskb + cmp
3401 {ISD::SMIN, MVT::v16i16, 3},
3402 {ISD::UMIN, MVT::v16i16, 3},
3410 {ISD::SMIN, MVT::v16i16, 1},
3411 {ISD::UMIN, MVT::v16i16, 1},
3532 {ISD::SMIN, MVT::v16i16, 6},
3533 {ISD::UMIN, MVT::v16i16, 6}, // FIXME: umin is cheaper than umax