Lines Matching refs:RB
74 unsigned getLoadStoreOp(const LLT &Ty, const RegisterBank &RB, unsigned Opc,
128 const TargetRegisterClass *getRegClass(LLT Ty, const RegisterBank &RB) const;
170 X86InstructionSelector::getRegClass(LLT Ty, const RegisterBank &RB) const {
171 if (RB.getID() == X86::GPRRegBankID) {
181 if (RB.getID() == X86::VECRRegBankID) {
396 const RegisterBank &RB,
405 if (X86::GPRRegBankID == RB.getID())
408 if (X86::GPRRegBankID == RB.getID())
411 if (X86::GPRRegBankID == RB.getID())
413 if (X86::VECRRegBankID == RB.getID())
421 if (X86::GPRRegBankID == RB.getID())
423 if (X86::VECRRegBankID == RB.getID())
510 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
530 unsigned NewOpc = getLoadStoreOp(Ty, RB, Opc, MemOp.getAlign());