Lines Matching defs:MIB
1287 MachineInstrBuilder MIB =
1294 MIB.addReg(0).addImm(1ULL << ShAmt)
1300 addRegOffset(MIB, InRegLEA, true, 1);
1304 addRegOffset(MIB, InRegLEA, true, -1);
1312 addRegOffset(MIB, InRegLEA, true, MI.getOperand(2).getImm());
1326 addRegReg(MIB, InRegLEA, true, InRegLEA, false);
1334 BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA2);
1335 InsMI2 = BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(TargetOpcode::COPY))
1338 addRegReg(MIB, InRegLEA, true, InRegLEA2, true);
1346 MachineInstr *NewMI = MIB;
1441 MachineInstrBuilder MIB =
1450 MIB.add(ImplicitOp);
1451 NewMI = MIB;
1477 MachineInstrBuilder MIB =
1482 MIB.add(ImplicitOp);
1484 NewMI = addOffset(MIB, 1);
1500 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1504 MIB.add(ImplicitOp);
1506 NewMI = addOffset(MIB, -1);
1543 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)).add(Dest);
1545 MIB.add(ImplicitOp);
1547 MIB.add(ImplicitOp2);
1549 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
1584 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1588 MIB.add(ImplicitOp);
1590 NewMI = addOffset(MIB, MI.getOperand(2));
1625 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1629 MIB.add(ImplicitOp);
1631 NewMI = addOffset(MIB, -Imm);
1645 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(),
1647 NewMI = addOffset(MIB, -Imm);
2935 auto MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opc));
2936 MIB->addOperand(TailCall.getOperand(0)); // Destination.
2937 MIB.addImm(0); // Stack offset (not used).
2938 MIB->addOperand(BranchCond[0]); // Condition.
2939 MIB.copyImplicitOps(TailCall); // Regmask and (imp-used) parameters.
2946 LiveRegs.stepForward(*MIB, Clobbers);
2948 MIB.addReg(C.first, RegState::Implicit);
2949 MIB.addReg(C.first, RegState::Implicit | RegState::Define);
4357 static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
4360 Register Reg = MIB.getReg(0);
4361 MIB->setDesc(Desc);
4365 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
4367 assert(MIB.getReg(1) == Reg &&
4368 MIB.getReg(2) == Reg && "Misplaced operand");
4378 static bool Expand2AddrKreg(MachineInstrBuilder &MIB,
4381 MIB->setDesc(Desc);
4382 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
4386 static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
4388 MachineBasicBlock &MBB = *MIB->getParent();
4389 DebugLoc DL = MIB->getDebugLoc();
4390 Register Reg = MIB.getReg(0);
4393 BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
4398 MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
4399 MIB.addReg(Reg);
4404 static bool ExpandMOVImmSExti8(MachineInstrBuilder &MIB,
4407 MachineBasicBlock &MBB = *MIB->getParent();
4408 DebugLoc DL = MIB->getDebugLoc();
4409 int64_t Imm = MIB->getOperand(1).getImm();
4411 MachineBasicBlock::iterator I = MIB.getInstr();
4416 assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||
4417 MIB->getOpcode() == X86::MOV32ImmSExti8);
4423 MIB->setDesc(TII.get(MIB->getOpcode() ==
4432 MIB->setDesc(TII.get(X86::POP64r));
4433 MIB->getOperand(0)
4434 .setReg(getX86SubSuperRegister(MIB.getReg(0), 64));
4436 assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
4439 MIB->setDesc(TII.get(X86::POP32r));
4441 MIB->RemoveOperand(1);
4442 MIB->addImplicitDefUseOperands(*MBB.getParent());
4462 static void expandLoadStackGuard(MachineInstrBuilder &MIB,
4464 MachineBasicBlock &MBB = *MIB->getParent();
4465 DebugLoc DL = MIB->getDebugLoc();
4466 Register Reg = MIB.getReg(0);
4468 cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
4474 MachineBasicBlock::iterator I = MIB.getInstr();
4479 MIB->setDebugLoc(DL);
4480 MIB->setDesc(TII.get(X86::MOV64rm));
4481 MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
4484 static bool expandXorFP(MachineInstrBuilder &MIB, const TargetInstrInfo &TII) {
4485 MachineBasicBlock &MBB = *MIB->getParent();
4490 MIB->getOpcode() == X86::XOR64_FP ? X86::XOR64rr : X86::XOR32rr;
4491 MIB->setDesc(TII.get(XorOp));
4492 MIB.addReg(TRI->getFrameRegister(MF), RegState::Undef);
4499 static bool expandNOVLXLoad(MachineInstrBuilder &MIB,
4504 Register DestReg = MIB.getReg(0);
4508 MIB->setDesc(LoadDesc);
4511 MIB->setDesc(BroadcastDesc);
4514 MIB->getOperand(0).setReg(DestReg);
4522 static bool expandNOVLXStore(MachineInstrBuilder &MIB,
4527 Register SrcReg = MIB.getReg(X86::AddrNumOperands);
4531 MIB->setDesc(StoreDesc);
4534 MIB->setDesc(ExtractDesc);
4537 MIB->getOperand(X86::AddrNumOperands).setReg(SrcReg);
4538 MIB.addImm(0x0); // Append immediate to extract from the lower bits.
4544 static bool expandSHXDROT(MachineInstrBuilder &MIB, const MCInstrDesc &Desc) {
4545 MIB->setDesc(Desc);
4546 int64_t ShiftAmt = MIB->getOperand(2).getImm();
4548 MIB->RemoveOperand(2);
4550 MIB.addReg(MIB.getReg(1),
4551 getUndefRegState(MIB->getOperand(1).isUndef()));
4553 MIB.addImm(ShiftAmt);
4559 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
4562 return Expand2AddrUndef(MIB, get(X86::XOR32rr));
4564 return expandMOV32r1(MIB, *this, /*MinusOne=*/ false);
4566 return expandMOV32r1(MIB, *this, /*MinusOne=*/ true);
4569 return ExpandMOVImmSExti8(MIB, *this, Subtarget);
4571 return Expand2AddrUndef(MIB, get(X86::SBB32rr));
4573 return Expand2AddrUndef(MIB, get(X86::SBB64rr));
4575 return Expand2AddrUndef(MIB, get(X86::MMX_PXORirr));
4580 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
4584 Register SrcReg = MIB.getReg(0);
4586 MIB->getOperand(0).setReg(XReg);
4587 Expand2AddrUndef(MIB, get(X86::VXORPSrr));
4588 MIB.addReg(SrcReg, RegState::ImplicitDefine);
4596 Register SrcReg = MIB.getReg(0);
4599 return Expand2AddrUndef(MIB,
4604 MIB->getOperand(0).setReg(SrcReg);
4605 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4610 Register SrcReg = MIB.getReg(0);
4614 MIB->getOperand(0).setReg(XReg);
4615 Expand2AddrUndef(MIB,
4617 MIB.addReg(SrcReg, RegState::ImplicitDefine);
4624 MIB->getOperand(0).setReg(ZReg);
4626 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4629 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
4631 return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
4633 Register Reg = MIB.getReg(0);
4635 MIB->setDesc(get(X86::VCMPPSYrri));
4636 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xf);
4640 Register Reg = MIB.getReg(0);
4641 MIB->setDesc(get(X86::VPTERNLOGDZrri));
4644 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef)
4650 Register Reg = MIB.getReg(0);
4651 Register MaskReg = MIB.getReg(1);
4652 unsigned MaskState = getRegState(MIB->getOperand(1));
4656 MIB->setDesc(get(Opc));
4659 MIB.addReg(Reg, RegState::Undef).addReg(MaskReg, MaskState)
4664 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSrm),
4667 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSrm),
4670 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSYrm),
4673 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSYrm),
4676 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSmr),
4679 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSmr),
4682 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSYmr),
4685 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSYmr),
4688 Register Reg = MIB.getReg(0);
4691 MIB->getOperand(0).setReg(Reg32);
4692 MIB.addReg(Reg, RegState::ImplicitDefine);
4703 case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0);
4704 case X86::KSET0D: return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0);
4705 case X86::KSET0Q: return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0);
4706 case X86::KSET1W: return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0);
4707 case X86::KSET1D: return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0);
4708 case X86::KSET1Q: return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0);
4710 expandLoadStackGuard(MIB, *this);
4714 return expandXorFP(MIB, *this);
4715 case X86::SHLDROT32ri: return expandSHXDROT(MIB, get(X86::SHLD32rri8));
4716 case X86::SHLDROT64ri: return expandSHXDROT(MIB, get(X86::SHLD64rri8));
4717 case X86::SHRDROT32ri: return expandSHXDROT(MIB, get(X86::SHRD32rri8));
4718 case X86::SHRDROT64ri: return expandSHXDROT(MIB, get(X86::SHRD64rri8));
4719 case X86::ADD8rr_DB: MIB->setDesc(get(X86::OR8rr)); break;
4720 case X86::ADD16rr_DB: MIB->setDesc(get(X86::OR16rr)); break;
4721 case X86::ADD32rr_DB: MIB->setDesc(get(X86::OR32rr)); break;
4722 case X86::ADD64rr_DB: MIB->setDesc(get(X86::OR64rr)); break;
4723 case X86::ADD8ri_DB: MIB->setDesc(get(X86::OR8ri)); break;
4724 case X86::ADD16ri_DB: MIB->setDesc(get(X86::OR16ri)); break;
4725 case X86::ADD32ri_DB: MIB->setDesc(get(X86::OR32ri)); break;
4726 case X86::ADD64ri32_DB: MIB->setDesc(get(X86::OR64ri32)); break;
4727 case X86::ADD16ri8_DB: MIB->setDesc(get(X86::OR16ri8)); break;
4728 case X86::ADD32ri8_DB: MIB->setDesc(get(X86::OR32ri8)); break;
4729 case X86::ADD64ri8_DB: MIB->setDesc(get(X86::OR64ri8)); break;
5180 static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
5187 MIB.add(MOs[i]);
5188 addOffset(MIB, PtrOffset);
5196 MIB.addDisp(MO, PtrOffset);
5198 MIB.add(MO);
5239 MachineInstrBuilder MIB(MF, NewMI);
5240 addOperands(MIB, MOs);
5246 MIB.add(MO);
5250 MIB.add(MO);
5258 return MIB;
5269 MachineInstrBuilder MIB(MF, NewMI);
5275 addOperands(MIB, MOs, PtrOffset);
5277 MIB.add(MO);
5290 return MIB;
5297 MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
5299 addOperands(MIB, MOs);
5300 return MIB.addImm(0);
6196 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), Reg);
6198 MIB.add(AddrOps[i]);
6199 MIB.setMemRefs(MMOs);
6200 NewMIs.push_back(MIB);
6214 MachineInstrBuilder MIB(MF, DataMI);
6217 MIB.addReg(Reg, RegState::Define);
6219 MIB.add(BeforeOp);
6221 MIB.addReg(Reg);
6223 MIB.add(AfterOp);
6225 MIB.addReg(ImpOp.getReg(),
6271 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
6273 MIB.add(AddrOps[i]);
6274 MIB.addReg(Reg, RegState::Kill);
6275 MIB.setMemRefs(MMOs);
6276 NewMIs.push_back(MIB);