Lines Matching refs:shl
443 // 64-bit shl, sra, srl (iff 32-bit x86)
5170 // convert this to shl+add/sub and then still have to type legalize those ops.
5178 // If vector multiply is legal, assume that's faster than shl + add/sub.
5185 // shl+add, shl+sub, shl+add+neg
5342 // Pre-AVX2 vector codegen for this pattern is best for variant with 'shl'.
24085 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
27045 // Optimize shl/srl/sra with constant shift amount.
27240 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
32570 // shl vreg2
37150 APInt DemandedSrc = DemandedElts.shl(ShiftAmt);
40389 // vsel ((X & C) == 0), LHS, RHS --> vsel ((shl X, C') < 0), RHS, LHS
41405 // mul x, 11 => add ((shl (mul x, 5), 1), x)
41408 // mul x, 21 => add ((shl (mul x, 5), 2), x)
41411 // mul x, 41 => add ((shl (mul x, 5), 3), x)
41414 // mul x, 22 => add (add ((shl (mul x, 5), 2), x), x)
41418 // mul x, 19 => add ((shl (mul x, 9), 1), x)
41421 // mul x, 37 => add ((shl (mul x, 9), 2), x)
41424 // mul x, 73 => add ((shl (mul x, 9), 3), x)
41427 // mul x, 13 => add ((shl (mul x, 3), 2), x)
41430 // mul x, 23 => sub ((shl (mul x, 3), 3), x)
41664 // (mul x, 2^N + 1) => (add (shl x, N), x)
41675 // (mul x, 2^N - 1) => (sub (shl x, N), x)
41685 // (mul x, 2^N + 2) => (add (add (shl x, N), x), x)
41692 // (mul x, 2^N - 2) => (sub (sub (shl x, N), x), x)
41768 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
41786 // (shl (and (setcc_c), c1), c2) -> i32 0x0001FFFE
41806 // shl.
41807 // (shl V, 1) -> add V,V
41831 // fold (ashr (shl, a, [56,48,32,24,16]), SarConst)
41832 // into (shl, (sext (a), [56,48,32,24,16] - SarConst)) or
45893 // other 'add' or 'shl' instruction.
49037 // 8-bit multiply/shl is probably not cheaper than 32-bit multiply/shl, and
49038 // we have specializations to turn 32-bit multiply/shl into LEA or other ops.
49134 // Look out for (store (shl (load), x)).