Lines Matching refs:IsLP64
52 IsLP64 = STI.isTarget64BitLP64();
104 static unsigned getSUBriOpcode(bool IsLP64, int64_t Imm) {
105 if (IsLP64) {
116 static unsigned getADDriOpcode(bool IsLP64, int64_t Imm) {
117 if (IsLP64) {
128 static unsigned getSUBrrOpcode(bool IsLP64) {
129 return IsLP64 ? X86::SUB64rr : X86::SUB32rr;
132 static unsigned getADDrrOpcode(bool IsLP64) {
133 return IsLP64 ? X86::ADD64rr : X86::ADD32rr;
136 static unsigned getANDriOpcode(bool IsLP64, int64_t Imm) {
137 if (IsLP64) {
147 static unsigned getLEArOpcode(bool IsLP64) {
148 return IsLP64 ? X86::LEA64r : X86::LEA32r;
2635 GetScratchRegister(bool Is64Bit, bool IsLP64, const MachineFunction &MF, bool Primary) {
2647 if (IsLP64)
2683 unsigned ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
2729 allocMBB->addLiveIn(IsLP64 ? X86::R10 : X86::R10D);
2742 TlsOffset = IsLP64 ? 0x70 : 0x40;
2760 ScratchReg = IsLP64 ? X86::RSP : X86::ESP;
2762 BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::LEA64r : X86::LEA64_32r), ScratchReg).addReg(X86::RSP)
2765 BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::CMP64rm : X86::CMP32rm)).addReg(ScratchReg)
2803 ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, true);
2807 ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, false);
2845 const unsigned RegAX = IsLP64 ? X86::RAX : X86::EAX;
2846 const unsigned Reg10 = IsLP64 ? X86::R10 : X86::R10D;
2847 const unsigned Reg11 = IsLP64 ? X86::R11 : X86::R11D;
2848 const unsigned MOVrr = IsLP64 ? X86::MOV64rr : X86::MOV32rr;
2849 const unsigned MOVri = IsLP64 ? X86::MOV64ri : X86::MOV32ri;
3069 ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);