Lines Matching defs:DL
303 MVT WebAssemblyTargetLowering::getScalarShiftAmountTy(const DataLayout & /*DL*/,
326 static MachineBasicBlock *LowerFPToInt(MachineInstr &MI, DebugLoc DL,
383 BuildMI(BB, DL, TII.get(Abs), Tmp0).addReg(InReg);
385 BuildMI(BB, DL, TII.get(FConst), Tmp1)
387 BuildMI(BB, DL, TII.get(LT), CmpReg).addReg(Tmp0).addReg(Tmp1);
395 BuildMI(BB, DL, TII.get(FConst), Tmp1)
397 BuildMI(BB, DL, TII.get(GE), SecondCmpReg).addReg(Tmp0).addReg(Tmp1);
398 BuildMI(BB, DL, TII.get(And), AndReg).addReg(CmpReg).addReg(SecondCmpReg);
402 BuildMI(BB, DL, TII.get(Eqz), EqzReg).addReg(CmpReg);
406 BuildMI(BB, DL, TII.get(WebAssembly::BR_IF)).addMBB(TrueMBB).addReg(EqzReg);
407 BuildMI(FalseMBB, DL, TII.get(LoweredOpcode), FalseReg).addReg(InReg);
408 BuildMI(FalseMBB, DL, TII.get(WebAssembly::BR)).addMBB(DoneMBB);
409 BuildMI(TrueMBB, DL, TII.get(IConst), TrueReg).addImm(Substitute);
410 BuildMI(*DoneMBB, DoneMBB->begin(), DL, TII.get(TargetOpcode::PHI), OutReg)
420 DebugLoc DL, MachineBasicBlock *BB,
443 MachineInstrBuilder MIB(MF, MF.CreateMachineInstr(MCID, DL));
474 DebugLoc DL = MI.getDebugLoc();
480 return LowerFPToInt(MI, DL, BB, TII, false, false, false,
483 return LowerFPToInt(MI, DL, BB, TII, true, false, false,
486 return LowerFPToInt(MI, DL, BB, TII, false, true, false,
489 return LowerFPToInt(MI, DL, BB, TII, true, true, false,
492 return LowerFPToInt(MI, DL, BB, TII, false, false, true,
495 return LowerFPToInt(MI, DL, BB, TII, true, false, true,
498 return LowerFPToInt(MI, DL, BB, TII, false, true, true,
501 return LowerFPToInt(MI, DL, BB, TII, true, true, true,
505 return LowerCallResults(MI, DL, BB, TII);
564 bool WebAssemblyTargetLowering::isLegalAddressingMode(const DataLayout &DL,
611 EVT WebAssemblyTargetLowering::getSetCCResultType(const DataLayout &DL,
672 static void fail(const SDLoc &DL, SelectionDAG &DAG, const char *Msg) {
675 DiagnosticInfoUnsupported(MF.getFunction(), Msg, DL.getDebugLoc()));
697 SDLoc DL = CLI.DL;
705 fail(DL, DAG,
709 fail(DL, DAG, "WebAssembly doesn't support patch point yet");
714 fail(DL, DAG, Msg);
784 fail(DL, DAG, "WebAssembly hasn't implemented nest arguments");
786 fail(DL, DAG, "WebAssembly hasn't implemented inalloca arguments");
788 fail(DL, DAG, "WebAssembly hasn't implemented cons regs arguments");
790 fail(DL, DAG, "WebAssembly hasn't implemented cons regs last arguments");
797 DAG.getConstant(Out.Flags.getByValSize(), DL, MVT::i32);
800 Chain, DL, FINode, OutVal, SizeNode, Out.Flags.getNonZeroByValAlign(),
875 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, FINode,
876 DAG.getConstant(Offset, DL, PtrVT));
878 DAG.getStore(Chain, DL, Arg, Add,
882 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
884 FINode = DAG.getIntPtrConstant(0, DL);
892 Callee = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
895 Callee = DAG.getNode(WebAssemblyISD::Wrapper, DL,
917 fail(DL, DAG, "WebAssembly hasn't implemented inalloca return values");
919 fail(DL, DAG, "WebAssembly hasn't implemented cons regs return values");
921 fail(DL, DAG,
931 return DAG.getNode(WebAssemblyISD::RET_CALL, DL, NodeTys, Ops);
936 SDValue Res = DAG.getNode(WebAssemblyISD::CALL, DL, InTyList, Ops);
956 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
961 fail(DL, DAG, "WebAssembly doesn't support non-C calling conventions");
965 Chain = DAG.getNode(WebAssemblyISD::RETURN, DL, MVT::Other, RetOps);
973 fail(DL, DAG, "WebAssembly hasn't implemented inalloca results");
975 fail(DL, DAG, "WebAssembly hasn't implemented cons regs results");
977 fail(DL, DAG, "WebAssembly hasn't implemented cons regs last results");
985 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
988 fail(DL, DAG, "WebAssembly doesn't support non-C calling conventions");
1003 fail(DL, DAG, "WebAssembly hasn't implemented inalloca arguments");
1005 fail(DL, DAG, "WebAssembly hasn't implemented nest arguments");
1007 fail(DL, DAG, "WebAssembly hasn't implemented cons regs arguments");
1009 fail(DL, DAG, "WebAssembly hasn't implemented cons regs last arguments");
1012 InVals.push_back(In.Used ? DAG.getNode(WebAssemblyISD::ARGUMENT, DL, In.VT,
1014 DL, MVT::i32))
1042 Chain, DL, VarargVreg,
1043 DAG.getNode(WebAssemblyISD::ARGUMENT, DL, PtrVT,
1044 DAG.getTargetConstant(Ins.size(), DL, MVT::i32)));
1085 SDLoc DL(Op);
1104 fail(DL, DAG, "WebAssembly hasn't implemented computed gotos");
1144 SDLoc DL(Op);
1149 DL, VT, Src),
1152 ? DAG.getCopyToReg(Chain, DL, Reg, Copy)
1153 : DAG.getCopyToReg(Chain, DL, Reg, Copy,
1168 SDLoc DL(Op);
1171 fail(DL, DAG,
1183 {DAG.getConstant(Depth, DL, MVT::i32)}, CallOptions, DL)
1204 SDLoc DL(Op);
1210 fail(DL, DAG, "WebAssembly only expects the 0 address space");
1228 DAG.getNode(WebAssemblyISD::Wrapper, DL, PtrVT,
1232 WebAssemblyISD::WrapperPIC, DL, VT,
1233 DAG.getTargetGlobalAddress(GA->getGlobal(), DL, VT, GA->getOffset(),
1236 return DAG.getNode(ISD::ADD, DL, VT, BaseAddr, SymAddr);
1242 return DAG.getNode(WebAssemblyISD::Wrapper, DL, VT,
1243 DAG.getTargetGlobalAddress(GA->getGlobal(), DL, VT,
1250 SDLoc DL(Op);
1255 return DAG.getNode(WebAssemblyISD::Wrapper, DL, VT,
1271 SDLoc DL(Op);
1292 return DAG.getNode(WebAssemblyISD::BR_TABLE, DL, MVT::Other, Ops);
1297 SDLoc DL(Op);
1303 SDValue ArgN = DAG.getCopyFromReg(DAG.getEntryNode(), DL,
1305 return DAG.getStore(Op.getOperand(0), DL, ArgN, Op.getOperand(1),
1324 SDLoc DL(Op);
1337 return DAG.getNode(WebAssemblyISD::Wrapper, DL, VT,
1349 SDValue SymNode = DAG.getNode(WebAssemblyISD::Wrapper, DL, PtrVT,
1351 return DAG.getNode(WebAssemblyISD::THROW, DL,
1370 Ops[OpIdx++] = DAG.getConstant(0, DL, MVT::i32);
1375 return DAG.getNode(WebAssemblyISD::SHUFFLE, DL, Op.getValueType(), Ops);
1383 SDLoc DL(Op);
1415 DAG.getConstant(IndexVal * Scale, DL, Index->getValueType(0));
1417 ISD::EXTRACT_VECTOR_ELT, DL, Extract.getValueType(),
1419 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Op.getValueType(), NewExtract,
1425 SDLoc DL(Op);
1532 Result = DAG.getNode(WebAssemblyISD::SWIZZLE, DL, VecT, SwizzleSrc,
1545 ConstLanes.push_back(DAG.getConstantFP(0, DL, LaneT));
1547 ConstLanes.push_back(DAG.getConstant(0, DL, LaneT));
1550 Result = DAG.getBuildVector(VecT, DL, ConstLanes);
1561 WebAssemblyISD::LOAD_SPLAT, DL, DAG.getVTList(VecT),
1566 Result = DAG.getSplatBuildVector(VecT, DL, SplatValue);
1577 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VecT, Result, Lane,
1578 DAG.getConstant(I, DL, MVT::i32));
1587 SDLoc DL(Op);
1604 Ops[OpIdx++] = DAG.getConstant(ByteIndex, DL, MVT::i32);
1608 return DAG.getNode(WebAssemblyISD::SHUFFLE, DL, Op.getValueType(), Ops);
1613 SDLoc DL(Op);
1625 return DAG.getNode(ISD::SELECT_CC, DL, MVT::i64, LHS[I], RHS[I],
1626 DAG.getConstant(uint64_t(-1), DL, MVT::i64),
1627 DAG.getConstant(uint64_t(0), DL, MVT::i64), CC);
1629 return DAG.getBuildVector(Op->getValueType(0), DL,
1651 SDLoc DL(Op);
1653 SDValue Mask = DAG.getConstant(LaneT.getSizeInBits() - 1, DL, MVT::i32);
1662 DAG.getNode(ISD::AND, DL, MVT::i32, ShiftElements[i], Mask);
1665 ShiftedValue = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32,
1668 DAG.getNode(ShiftOpcode, DL, MVT::i32, ShiftedValue, MaskedShiftValue));
1670 return DAG.getBuildVector(Op.getValueType(), DL, UnrolledOps);
1675 SDLoc DL(Op);
1685 ShiftVal = DAG.getAnyExtOrTrunc(ShiftVal, DL, MVT::i32);
1702 return DAG.getNode(Opcode, DL, Op.getValueType(), Op.getOperand(0), ShiftVal);