Lines Matching refs:v4i32
107 addRegisterClass(MVT::v4i32, &SystemZ::VR128BitRegClass);
421 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
423 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
425 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
427 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
430 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v4i32, Legal);
432 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v4i32, Legal);
434 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i32, Legal);
436 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i32, Legal);
1417 case MVT::v4i32:
3781 Op = DAG.getNode(SystemZISD::VSUM, DL, MVT::v4i32, Op, Tmp);
5994 if (VT == MVT::v8i16 || VT == MVT::v4i32 || VT == MVT::v2i64)