Lines Matching refs:BitSize
2317 // CCMask says which comparison result is being tested and BitSize is
2320 static unsigned getTestUnderMaskCond(unsigned BitSize, unsigned CCMask,
2458 unsigned BitSize = NewC.Op0.getValueSizeInBits();
2465 (NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask,
2476 (NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask,
2483 NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask, MaskVal, CmpVal,
3799 int64_t BitSize = (int64_t)1 << Log2_32_Ceil(NumSignificantBits);
3800 BitSize = std::min(BitSize, OrigBitSize);
3808 // position larger than BitSize remain zero throughout.
3809 for (int64_t I = BitSize / 2; I >= 8; I = I / 2) {
3811 if (BitSize != OrigBitSize)
3813 DAG.getConstant(((uint64_t)1 << BitSize) - 1, DL, VT));
3818 if (BitSize > 8)
3820 DAG.getConstant(BitSize - 8, DL, VT));
3883 int64_t BitSize = NarrowVT.getSizeInBits();
3920 DAG.getConstant(32 - BitSize, DL, WideVT));
3924 DAG.getConstant(uint32_t(-1) >> BitSize, DL, WideVT));
3929 DAG.getConstant(BitSize, DL, WideVT) };
3936 DAG.getConstant(BitSize, DL, WideVT));
4011 int64_t BitSize = NarrowVT.getSizeInBits();
4032 NegBitShift, DAG.getConstant(BitSize, DL, WideVT) };
7319 // BitSize is the width of the field in bits, or 0 if this is a partword
7325 unsigned BitSize, bool Invert) const {
7330 bool IsSubWord = (BitSize < 32);
7342 BitSize = MI.getOperand(6).getImm();
7345 const TargetRegisterClass *RC = (BitSize <= 32 ?
7348 unsigned LOpcode = BitSize <= 32 ? SystemZ::L : SystemZ::LG;
7349 unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
7396 if (BitSize <= 32)
7397 // XILF with the upper BitSize bits set.
7399 .addReg(Tmp).addImm(-1U << (32 - BitSize));
7418 .addImm(32).addImm(31 + BitSize).addImm(32 - BitSize);
7440 // for when the current field should be kept. BitSize is the width of
7444 unsigned KeepOldMask, unsigned BitSize) const {
7449 bool IsSubWord = (BitSize < 32);
7460 BitSize = MI.getOperand(6).getImm();
7463 const TargetRegisterClass *RC = (BitSize <= 32 ?
7466 unsigned LOpcode = BitSize <= 32 ? SystemZ::L : SystemZ::LG;
7467 unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
7517 // %RotatedAltVal = RISBG %RotatedOldVal, %Src2, 32, 31 + BitSize, 0
7523 .addImm(32).addImm(31 + BitSize).addImm(0);
7573 int64_t BitSize = MI.getOperand(7).getImm();
7614 // %Dest = RLL %OldVal, BitSize(%BitShift)
7615 // ^^ The low BitSize bits contain the field
7617 // %RetryCmpVal = RISBG32 %CmpVal, %Dest, 32, 63-BitSize, 0
7618 // ^^ Replace the upper 32-BitSize bits of the
7635 .addReg(OldVal).addReg(BitShift).addImm(BitSize);
7637 .addReg(CmpVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
7647 // %RetrySwapVal = RISBG32 %SwapVal, %Dest, 32, 63-BitSize, 0
7648 // ^^ Replace the upper 32-BitSize bits of the new
7650 // %StoreVal = RLL %RetrySwapVal, -BitSize(%NegBitShift)
7657 .addReg(SwapVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
7659 .addReg(RetrySwapVal).addReg(NegBitShift).addImm(-BitSize);