Lines Matching refs:SP
36 SparcRegisterInfo::SparcRegisterInfo() : SparcGenRegisterInfo(SP::O7) {}
58 Reserved.set(SP::G1);
62 Reserved.set(SP::G2);
63 Reserved.set(SP::G3);
64 Reserved.set(SP::G4);
68 Reserved.set(SP::G5);
70 Reserved.set(SP::O6);
71 Reserved.set(SP::I6);
72 Reserved.set(SP::I7);
73 Reserved.set(SP::G0);
74 Reserved.set(SP::G6);
75 Reserved.set(SP::G7);
79 Reserved.set(SP::G0_G1);
81 Reserved.set(SP::G2_G3);
83 Reserved.set(SP::G4_G5);
85 Reserved.set(SP::O6_O7);
86 Reserved.set(SP::I6_I7);
87 Reserved.set(SP::G6_G7);
92 for (MCRegAliasIterator AI(SP::D16 + n, this, true); AI.isValid(); ++AI)
99 Reserved.set(SP::ASR1 + n);
108 return Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
132 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1)
137 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
140 MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false);
150 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1)
152 BuildMI(*MI.getParent(), II, dl, TII.get(SP::XORri), SP::G1)
153 .addReg(SP::G1).addImm(LOX10(Offset));
155 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
158 MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false);
183 if (MI.getOpcode() == SP::STQFri) {
186 Register SrcEvenReg = getSubReg(SrcReg, SP::sub_even64);
187 Register SrcOddReg = getSubReg(SrcReg, SP::sub_odd64);
189 BuildMI(*MI.getParent(), II, dl, TII.get(SP::STDFri))
192 MI.setDesc(TII.get(SP::STDFri));
195 } else if (MI.getOpcode() == SP::LDQFri) {
198 Register DestEvenReg = getSubReg(DestReg, SP::sub_even64);
199 Register DestOddReg = getSubReg(DestReg, SP::sub_odd64);
201 BuildMI(*MI.getParent(), II, dl, TII.get(SP::LDDFri), DestEvenReg)
205 MI.setDesc(TII.get(SP::LDDFri));
216 return SP::I6;
232 // If there's a reserved call frame, we can use SP to access locals.