Lines Matching refs:SP
35 : SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), RI(),
45 if (MI.getOpcode() == SP::LDri || MI.getOpcode() == SP::LDXri ||
46 MI.getOpcode() == SP::LDFri || MI.getOpcode() == SP::LDDFri ||
47 MI.getOpcode() == SP::LDQFri) {
64 if (MI.getOpcode() == SP::STri || MI.getOpcode() == SP::STXri ||
65 MI.getOpcode() == SP::STFri || MI.getOpcode() == SP::STDFri ||
66 MI.getOpcode() == SP::STQFri) {
143 static bool isUncondBranchOpcode(int Opc) { return Opc == SP::BA; }
146 return Opc == SP::FBCOND || Opc == SP::BCOND;
150 return Opc == SP::BINDrr || Opc == SP::BINDri;
255 BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);
263 BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC);
265 BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC);
269 BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB);
285 if (I->getOpcode() != SP::BA
286 && I->getOpcode() != SP::BCOND
287 && I->getOpcode() != SP::FBCOND)
314 const unsigned DW_SubRegsIdx[] = { SP::sub_even, SP::sub_odd };
315 const unsigned DFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd };
316 const unsigned QFP_DFP_SubRegsIdx[] = { SP::sub_even64, SP::sub_odd64 };
317 const unsigned QFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd,
318 SP::sub_odd64_then_sub_even,
319 SP::sub_odd64_then_sub_odd };
321 if (SP::IntRegsRegClass.contains(DestReg, SrcReg))
322 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0)
324 else if (SP::IntPairRegClass.contains(DestReg, SrcReg)) {
327 movOpc = SP::ORrr;
329 } else if (SP::FPRegsRegClass.contains(DestReg, SrcReg))
330 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
332 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) {
334 BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg)
340 movOpc = SP::FMOVS;
342 } else if (SP::QFPRegsRegClass.contains(DestReg, SrcReg)) {
345 BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg)
351 movOpc = SP::FMOVD;
357 movOpc = SP::FMOVS;
359 } else if (SP::ASRRegsRegClass.contains(DestReg) &&
360 SP::IntRegsRegClass.contains(SrcReg)) {
361 BuildMI(MBB, I, DL, get(SP::WRASRrr), DestReg)
362 .addReg(SP::G0)
364 } else if (SP::IntRegsRegClass.contains(DestReg) &&
365 SP::ASRRegsRegClass.contains(SrcReg)) {
366 BuildMI(MBB, I, DL, get(SP::RDASR), DestReg)
384 MIB.addReg(SP::G0);
409 if (RC == &SP::I64RegsRegClass)
410 BuildMI(MBB, I, DL, get(SP::STXri)).addFrameIndex(FI).addImm(0)
412 else if (RC == &SP::IntRegsRegClass)
413 BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0)
415 else if (RC == &SP::IntPairRegClass)
416 BuildMI(MBB, I, DL, get(SP::STDri)).addFrameIndex(FI).addImm(0)
418 else if (RC == &SP::FPRegsRegClass)
419 BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0)
421 else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
422 BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0)
424 else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
427 BuildMI(MBB, I, DL, get(SP::STQFri)).addFrameIndex(FI).addImm(0)
447 if (RC == &SP::I64RegsRegClass)
448 BuildMI(MBB, I, DL, get(SP::LDXri), DestReg).addFrameIndex(FI).addImm(0)
450 else if (RC == &SP::IntRegsRegClass)
451 BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0)
453 else if (RC == &SP::IntPairRegClass)
454 BuildMI(MBB, I, DL, get(SP::LDDri), DestReg).addFrameIndex(FI).addImm(0)
456 else if (RC == &SP::FPRegsRegClass)
457 BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0)
459 else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
460 BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0)
462 else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
465 BuildMI(MBB, I, DL, get(SP::LDQFri), DestReg).addFrameIndex(FI).addImm(0)
483 Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
488 BuildMI(FirstMBB, MBBI, dl, get(SP::GETPCX), GlobalBaseReg);
500 MI.setDesc(get(Subtarget.is64Bit() ? SP::LDXri : SP::LDri));
502 .addReg(SP::G7)