Lines Matching defs:Ops
950 SmallVector<SDValue, 8> Ops;
951 Ops.push_back(Chain);
952 Ops.push_back(Callee);
954 Ops.push_back(DAG.getTargetConstant(SRetArgSize, dl, MVT::i32));
956 Ops.push_back(DAG.getRegister(toCallerWindow(RegsToPass[i].first),
966 Ops.push_back(DAG.getRegisterMask(Mask));
969 Ops.push_back(InFlag);
971 Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, Ops);
1252 SmallVector<SDValue, 8> Ops;
1253 Ops.push_back(Chain);
1254 Ops.push_back(Callee);
1256 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1266 Ops.push_back(DAG.getRegisterMask(Mask));
1271 Ops.push_back(InGlue);
1275 Chain = DAG.getNode(SPISD::CALL, DL, NodeTys, Ops);
2065 SDValue Ops[] = {Chain,
2071 Chain = DAG.getNode(SPISD::TLS_CALL, DL, NodeTys, Ops);
2608 SDValue Ops[2] = { NewVal, Chain };
2609 return DAG.getMergeValues(Ops, dl);
2770 SDValue Ops[2] = {SDValue(InFP128,0), OutChain};
2771 return DAG.getMergeValues(Ops, dl);
2932 SDValue Ops[2] = { Dst, Carry };
2933 return DAG.getMergeValues(Ops, dl);
2982 SDValue Ops[2] = { BottomHalf, TopHalf } ;
2983 return DAG.getMergeValues(Ops, dl);
3226 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3227 /// vector. If it is invalid, don't add anything to Ops.
3231 std::vector<SDValue> &Ops,
3254 Ops.push_back(Result);
3257 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3371 SDValue Ops[] = { Lo, Hi };
3372 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops);