Lines Matching refs:SP
52 BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6)
53 .addReg(SP::O6).addImm(NumBytes);
64 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
66 BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
67 .addReg(SP::G1).addImm(LO10(NumBytes));
68 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
69 .addReg(SP::O6).addReg(SP::G1);
77 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
79 BuildMI(MBB, MBBI, dl, TII.get(SP::XORri), SP::G1)
80 .addReg(SP::G1).addImm(LOX10(NumBytes));
81 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
82 .addReg(SP::O6).addReg(SP::G1);
115 unsigned SAVEri = SP::SAVEri;
116 unsigned SAVErr = SP::SAVErr;
120 SAVEri = SP::ADDri;
121 SAVErr = SP::ADDrr;
156 unsigned regFP = RegInfo.getDwarfRegNum(SP::I6, true);
169 unsigned regInRA = RegInfo.getDwarfRegNum(SP::I7, true);
170 unsigned regOutRA = RegInfo.getDwarfRegNum(SP::O7, true);
182 regUnbiased = SP::G1;
184 BuildMI(MBB, MBBI, dl, TII.get(SP::ADDri), regUnbiased)
185 .addReg(SP::O6).addImm(Bias);
187 regUnbiased = SP::O6;
191 BuildMI(MBB, MBBI, dl, TII.get(SP::ANDNri), regUnbiased)
197 BuildMI(MBB, MBBI, dl, TII.get(SP::ADDri), SP::O6)
209 if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
213 emitSPAdjustment(MF, MBB, I, Size, SP::ADDrr, SP::ADDri);
226 assert(MBBI->getOpcode() == SP::RETL &&
229 BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
230 .addReg(SP::G0);
239 emitSPAdjustment(MF, MBB, MBBI, NumBytes, SP::ADDrr, SP::ADDri);
300 FrameReg = SP::O6; // %sp
308 for (unsigned reg = SP::I0; reg <= SP::I7; ++reg)
312 for (unsigned reg = SP::L0; reg <= SP::L7; ++reg)
326 || MRI.isPhysRegUsed(SP::L0) // Too many registers needed
327 || MRI.isPhysRegUsed(SP::O6) // %sp is used
334 for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
338 unsigned mapped_reg = reg - SP::I0 + SP::O0;
344 if ((reg - SP::I0) % 2 == 0) {
345 unsigned preg = (reg - SP::I0) / 2 + SP::I0_I1;
346 unsigned mapped_preg = preg - SP::I0_I1 + SP::O0_O1;
354 for (unsigned reg = SP::I0_I1; reg <= SP::I6_I7; ++reg) {
358 MBB->addLiveIn(reg - SP::I0_I1 + SP::O0_O1);
360 for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
364 MBB->addLiveIn(reg - SP::I0 + SP::O0);