Target/RISCV/RISCVISelLowering.cpp

81   MVT XLenVT = Subtarget.getXLenVT();
84   addRegisterClass(XLenVT, &RISCV::GPRRegClass);
97     setLoadExtAction(N, XLenVT, MVT::i1, Promote);
100   setOperationAction(ISD::DYNAMIC_STACKALLOC, XLenVT, Expand);
103   setOperationAction(ISD::BR_CC, XLenVT, Expand);
104   setOperationAction(ISD::SELECT, XLenVT, Custom);
105   setOperationAction(ISD::SELECT_CC, XLenVT, Expand);
127     setOperationAction(ISD::MUL, XLenVT, Expand);
128     setOperationAction(ISD::MULHS, XLenVT, Expand);
129     setOperationAction(ISD::MULHU, XLenVT, Expand);
130     setOperationAction(ISD::SDIV, XLenVT, Expand);
131     setOperationAction(ISD::UDIV, XLenVT, Expand);
132     setOperationAction(ISD::SREM, XLenVT, Expand);
133     setOperationAction(ISD::UREM, XLenVT, Expand);
143   setOperationAction(ISD::SDIVREM, XLenVT, Expand);
144   setOperationAction(ISD::UDIVREM, XLenVT, Expand);
145   setOperationAction(ISD::SMUL_LOHI, XLenVT, Expand);
146   setOperationAction(ISD::UMUL_LOHI, XLenVT, Expand);
148   setOperationAction(ISD::SHL_PARTS, XLenVT, Custom);
149   setOperationAction(ISD::SRL_PARTS, XLenVT, Custom);
150   setOperationAction(ISD::SRA_PARTS, XLenVT, Custom);
153     setOperationAction(ISD::ROTL, XLenVT, Expand);
154     setOperationAction(ISD::ROTR, XLenVT, Expand);
158     setOperationAction(ISD::BSWAP, XLenVT, Expand);
161     setOperationAction(ISD::CTTZ, XLenVT, Expand);
162     setOperationAction(ISD::CTLZ, XLenVT, Expand);
163     setOperationAction(ISD::CTPOP, XLenVT, Expand);
167     setOperationAction(ISD::BITREVERSE, XLenVT, Legal);
170     setOperationAction(ISD::FSHL, XLenVT, Legal);
171     setOperationAction(ISD::FSHR, XLenVT, Legal);
224   setOperationAction(ISD::GlobalAddress, XLenVT, Custom);
225   setOperationAction(ISD::BlockAddress, XLenVT, Custom);
226   setOperationAction(ISD::ConstantPool, XLenVT, Custom);
228   setOperationAction(ISD::GlobalTLSAddress, XLenVT, Custom);
532   MVT XLenVT = Subtarget.getXLenVT();
544                        DAG.getConstant(Offset, DL, XLenVT));
568   MVT XLenVT = Subtarget.getXLenVT();
580     SDValue TPReg = DAG.getRegister(RISCV::X4, XLenVT);
596   SDValue TPReg = DAG.getRegister(RISCV::X4, XLenVT);
641   MVT XLenVT = Subtarget.getXLenVT();
665                        DAG.getConstant(Offset, DL, XLenVT));
674   MVT XLenVT = Subtarget.getXLenVT();
676   // If the result type is XLenVT and CondV is the output of a SETCC node
677   // which also operated on XLenVT inputs, then merge the SETCC node into the
682   if (Op.getSimpleValueType() == XLenVT && CondV.getOpcode() == ISD::SETCC &&
683       CondV.getOperand(0).getSimpleValueType() == XLenVT) {
691     SDValue TargetCC = DAG.getConstant(CCVal, DL, XLenVT);
700   SDValue Zero = DAG.getConstant(0, DL, XLenVT);
701   SDValue SetNE = DAG.getConstant(ISD::SETNE, DL, XLenVT);
753   MVT XLenVT = Subtarget.getXLenVT();
773   Register Reg = MF.addLiveIn(RI.getRARegister(), getRegClassFor(XLenVT));
774   return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, XLenVT);
1550   MVT XLenVT = XLen == 32 ? MVT::i32 : MVT::i64;
1590     LocVT = XLenVT;
1646     LocVT = XLenVT;
1699   assert((!UseGPRForF32 || !UseGPRForF64 || LocVT == XLenVT) &&
1700          "Expected an XLenVT at this stage");
1993   MVT XLenVT = Subtarget.getXLenVT();
2083       SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, XLenVT);
2194   MVT XLenVT = Subtarget.getXLenVT();
2234     SDValue SizeNode = DAG.getConstant(Size, DL, XLenVT);