Target/RISCV/RISCVISelLowering.cpp

45 RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
263 EVT RISCVTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
270 bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
298 bool RISCVTargetLowering::isLegalAddressingMode(const DataLayout &DL,
324 bool RISCVTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
328 bool RISCVTargetLowering::isLegalAddImmediate(int64_t Imm) const {
335 bool RISCVTargetLowering::isTruncateFree(Type *SrcTy, Type *DstTy) const {
343 bool RISCVTargetLowering::isTruncateFree(EVT SrcVT, EVT DstVT) const {
352 bool RISCVTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
366 bool RISCVTargetLowering::isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const {
370 bool RISCVTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
381 bool RISCVTargetLowering::hasBitPreservingFPLogic(EVT VT) const {
425 SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
486 SDValue RISCVTargetLowering::getAddr(NodeTy *N, SelectionDAG &DAG,
526 SDValue RISCVTargetLowering::lowerGlobalAddress(SDValue Op,
548 SDValue RISCVTargetLowering::lowerBlockAddress(SDValue Op,
555 SDValue RISCVTargetLowering::lowerConstantPool(SDValue Op,
562 SDValue RISCVTargetLowering::getStaticTLSAddr(GlobalAddressSDNode *N,
603 SDValue RISCVTargetLowering::getDynamicTLSAddr(GlobalAddressSDNode *N,
635 SDValue RISCVTargetLowering::lowerGlobalTLSAddress(SDValue Op,
669 SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
709 SDValue RISCVTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
724 SDValue RISCVTargetLowering::lowerFRAMEADDR(SDValue Op,
747 SDValue RISCVTargetLowering::lowerRETURNADDR(SDValue Op,
777 SDValue RISCVTargetLowering::lowerShiftLeftParts(SDValue Op,
816 SDValue RISCVTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
868 SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
930 void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
1019 SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
1118 bool RISCVTargetLowering::isDesirableToCommuteWithShift(
1164 unsigned RISCVTargetLowering::ComputeNumSignBitsForTargetNode(
1446 RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1716 void RISCVTargetLowering::analyzeInputArgs(
1742 void RISCVTargetLowering::analyzeOutputArgs(
1963 SDValue RISCVTargetLowering::LowerFormalArguments(
2109 bool RISCVTargetLowering::isEligibleForTailCallOptimization(
2181 SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
2456 bool RISCVTargetLowering::CanLowerReturn(
2473 RISCVTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2571 void RISCVTargetLowering::validateCCReservedRegs(
2584 bool RISCVTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
2588 const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const {
2634 RISCVTargetLowering::ConstraintType
2635 RISCVTargetLowering::getConstraintType(StringRef Constraint) const {
2654 RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
2768 RISCVTargetLowering::getInlineAsmMemConstraint(StringRef ConstraintCode) const {
2782 void RISCVTargetLowering::LowerAsmOperandForConstraint(
2820 Instruction *RISCVTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
2830 Instruction *RISCVTargetLowering::emitTrailingFence(IRBuilder<> &Builder,
2839 RISCVTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
2903 Value *RISCVTargetLowering::emitMaskedAtomicRMWIntrinsic(
2947 RISCVTargetLowering::shouldExpandAtomicCmpXchgInIR(
2955 Value *RISCVTargetLowering::emitMaskedAtomicCmpXchgIntrinsic(
2977 Register RISCVTargetLowering::getExceptionPointerRegister(
2982 Register RISCVTargetLowering::getExceptionSelectorRegister(
2987 bool RISCVTargetLowering::shouldExtendTypeInLibCall(EVT Type) const {
2997 bool RISCVTargetLowering::decomposeMulByConstant(LLVMContext &Context, EVT VT,
3021 RISCVTargetLowering::getRegisterByName(const char *RegName, LLT VT,