Lines Matching defs:Ops
2877 SDValue Ops[] = { GA, Reg };
2879 PPCISD::TOC_ENTRY, dl, DAG.getVTList(VT, MVT::Other), Ops, VT,
5521 buildCallOperands(SmallVectorImpl<SDValue> &Ops,
5532 Ops.push_back(Chain);
5536 Ops.push_back(Callee);
5556 Ops.push_back(AddTOC);
5561 Ops.push_back(DAG.getRegister(Subtarget.getEnvironmentPointerRegister(),
5567 Ops.push_back(DAG.getRegister(IsPPC64 ? PPC::CTR8 : PPC::CTR, RegVT));
5572 Ops.push_back(DAG.getConstant(SPDiff, dl, MVT::i32));
5577 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
5585 Ops.push_back(DAG.getRegister(Subtarget.getTOCPointerRegister(), RegVT));
5589 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
5596 Ops.push_back(DAG.getRegisterMask(Mask));
5600 Ops.push_back(Glue);
5627 SmallVector<SDValue, 8> Ops;
5628 buildCallOperands(Ops, CFlags, dl, DAG, RegsToPass, Glue, Chain, Callee,
5648 return DAG.getNode(CallOpc, dl, MVT::Other, Ops);
5652 Chain = DAG.getNode(CallOpc, dl, ReturnTypes, Ops);
5975 SDValue Ops[] = { Chain, InFlag };
5978 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
7847 SDValue Ops[2] = {Chain, FPSIdx};
7849 return DAG.getNode(PPCISD::DYNAREAOFFSET, dl, VTs, Ops);
7940 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
7943 return DAG.getNode(PPCISD::PROBED_ALLOCA, dl, VTs, Ops);
7944 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
7994 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
7995 return DAG.getMergeValues(Ops, dl);
8248 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
8250 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
8505 SmallVector<SDValue, 16> Ops(NumConcat);
8506 Ops[0] = Vec;
8509 Ops[i] = UndefVec;
8511 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WideVT, Ops);
8691 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
8694 Ops, MVT::i32, MMO);
8701 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
8704 Ops, MVT::i32, MMO);
8734 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
8738 Ops, MVT::i32, MMO);
8787 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
8791 Ops, MVT::i32, MMO);
9037 int Ops[16];
9039 Ops[i] = i + Amt;
9040 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
9210 SDValue Ops[] = {DAG.getEntryNode(), CPIdx};
9213 PPCISD::QVLFSb, dl, VTs, Ops, MVT::v4f32,
9251 SDValue Ops[] = {StoreChain,
9257 dl, VTs, Ops, MVT::v4i32, PtrInfo);
9310 SDValue Ops[] = {
9318 Ops, LD->getMemoryVT(), LD->getMemOperand());
9950 SDValue Ops[] = {
9959 Ops, LD->getMemoryVT(), LD->getMemOperand());
10519 SDValue Ops[] = {
10525 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
10630 SmallVector<SDValue, 4> Ops;
10632 Ops.push_back(AtomicNode->getOperand(i));
10633 Ops[2] = NewCmpOp;
10638 return DAG.getMemIntrinsicNode(NodeTy, dl, Tys, Ops, MemVT, MMO);
10723 SDValue Ops[] = {StoreChain,
10729 dl, VTs, Ops, MVT::v4i32, PtrInfo);
10921 SDValue Ops[] = {StoreChain,
10927 dl, VTs, Ops, MVT::v4i32, PtrInfo);
11004 int Ops[16];
11007 Ops[i*2 ] = 2*i;
11008 Ops[i*2+1] = 2*i+16;
11010 Ops[i*2 ] = 2*i+1;
11011 Ops[i*2+1] = 2*i+1+16;
11015 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops);
11017 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
13500 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
13505 if (isa<ConstantSDNode>(Ops[C+i]))
13506 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
13509 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
13747 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
13752 if (!isa<ConstantSDNode>(Ops[C+i]))
13754 if (Ops[C+i].getValueType() == N->getValueType(0))
13758 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
13760 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
13762 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
13771 Ops[0] = DAG.getNode(ISD::TRUNCATE, dl, SI0->second, Ops[0]);
13774 Ops[1] = DAG.getNode(ISD::TRUNCATE, dl, SI1->second, Ops[1]);
13778 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
13874 SmallVector<SDValue, 4> Ops;
13906 Ops.push_back(DAG.getUNDEF(SrcVT));
13911 Ops.push_back(Trunc);
13914 Ops.push_back(In.isUndef() ? DAG.getUNDEF(SrcVT) : In.getOperand(0));
13925 SDValue BV = DAG.getBuildVector(NewVT, dl, Ops);
14014 SmallVector<int, 16> Ops;
14016 Ops.push_back(i);
14019 DAG.getUNDEF(N->getValueType(0)), Ops);
14280 SDValue Ops[] = { LDN->getChain(), LDN->getBasePtr(), WidthConst };
14283 Ops, MVT::i8, LDN->getMemOperand());
14528 SDValue Ops[] = { N->getOperand(0), Val, N->getOperand(2),
14533 DAG.getVTList(MVT::Other), Ops,
14901 SDValue Ops[] = {
14906 Ops, cast<StoreSDNode>(N)->getMemoryVT(),
15331 SDValue Ops[] = {
15340 Ops, LD->getMemoryVT(), LD->getMemOperand());
15489 SDValue Ops[] = {
15495 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
15843 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
15844 /// vector. If it is invalid, don't add anything to Ops.
15847 std::vector<SDValue>&Ops,
15911 Ops.push_back(Result);
15916 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);