Lines Matching refs:Base
214 uint64_t Base = Imm >> 16;
217 assert(Base < 32 && "Invalid base register");
228 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
235 Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base]));
240 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
249 uint64_t Base = Imm >> 14;
252 assert(Base < 32 && "Invalid base register");
256 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
258 Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base]));
261 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
270 uint64_t Base = Imm >> 12;
273 assert(Base < 32 && "Invalid base register");
276 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
285 uint64_t Base = Imm >> 34;
288 assert(Base < 32 && "Invalid base register");
291 return decodeImmZeroOperand(Inst, Base, Address, Decoder);
299 uint64_t Base = Imm >> 34;
302 assert(Base < 32 && "Invalid base register");
305 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
314 uint64_t Base = Imm >> 5;
317 assert(Base < 32 && "Invalid base register");
320 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
329 uint64_t Base = Imm >> 5;
332 assert(Base < 32 && "Invalid base register");
335 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
344 uint64_t Base = Imm >> 5;
347 assert(Base < 32 && "Invalid base register");
350 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));