Lines Matching refs:TII
61 const MipsInstrInfo &TII;
83 : InstructionSelector(), TM(TM), STI(STI), TII(*STI.getInstrInfo()),
113 LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
152 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI);
158 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI);
165 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI);
173 if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI))
175 if (!constrainSelectedInstRegOperands(*ORi, TII, TRI, RBI))
261 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opc))
266 if (!constrainSelectedInstRegOperands(*NewInst, TII, TRI, RBI))
275 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opc))
281 if (!constrainSelectedInstRegOperands(*NewInst, TII, TRI, RBI))
301 MachineInstr *Mul = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MUL))
305 if (!constrainSelectedInstRegOperands(*Mul, TII, TRI, RBI))
325 PseudoMULTu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMULTu))
329 if (!constrainSelectedInstRegOperands(*PseudoMULTu, TII, TRI, RBI))
332 PseudoMove = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMFHI))
335 if (!constrainSelectedInstRegOperands(*PseudoMove, TII, TRI, RBI))
342 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu))
350 I.setDesc(TII.get(COPY));
354 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu))
361 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::BNE))
374 MachineInstr *SLL = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SLL))
378 if (!constrainSelectedInstRegOperands(*SLL, TII, TRI, RBI))
382 MachineInstr *ADDu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu))
386 if (!constrainSelectedInstRegOperands(*ADDu, TII, TRI, RBI))
391 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW))
397 if (!constrainSelectedInstRegOperands(*LW, TII, TRI, RBI))
403 MachineInstr *ADDu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu))
408 if (!constrainSelectedInstRegOperands(*ADDu, TII, TRI, RBI))
413 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoIndirectBranch))
415 if (!constrainSelectedInstRegOperands(*Branch, TII, TRI, RBI))
422 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoIndirectBranch))
435 I.setDesc(TII.get(TargetOpcode::PHI));
481 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::IMPLICIT_DEF))
501 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(NewOpc))
518 TII.get(IsSigned ? Mips::PseudoSDIV : Mips::PseudoUDIV))
522 if (!constrainSelectedInstRegOperands(*PseudoDIV, TII, TRI, RBI))
526 TII.get(IsDiv ? Mips::PseudoMFLO : Mips::PseudoMFHI))
529 if (!constrainSelectedInstRegOperands(*PseudoMove, TII, TRI, RBI))
537 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MOVN_I_I))
557 MachineInstr *ExtractLo = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode))
561 if (!constrainSelectedInstRegOperands(*ExtractLo, TII, TRI, RBI))
564 MachineInstr *ExtractHi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode))
568 if (!constrainSelectedInstRegOperands(*ExtractHi, TII, TRI, RBI))
576 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::IMPLICIT_DEF))
605 if (!MTC1.constrainAllUses(TII, TRI, RBI))
620 if (!PairF64.constrainAllUses(TII, TRI, RBI))
632 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(FABSOpcode))
651 MachineInstr *Trunc = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode))
654 if (!constrainSelectedInstRegOperands(*Trunc, TII, TRI, RBI))
657 MachineInstr *Move = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MFC1))
660 if (!constrainSelectedInstRegOperands(*Move, TII, TRI, RBI))
669 MachineInstr *LWGOT = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW))
685 if (!constrainSelectedInstRegOperands(*LWGOT, TII, TRI, RBI))
693 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu))
698 if (!constrainSelectedInstRegOperands(*ADDiu, TII, TRI, RBI))
704 MachineInstr *LUi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi))
708 if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI))
712 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu))
717 if (!constrainSelectedInstRegOperands(*ADDiu, TII, TRI, RBI))
725 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW))
735 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi))
814 if (!MIB.constrainAllUses(TII, TRI, RBI))
872 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu))
881 MachineInstr *FCMP = BuildMI(MBB, I, I.getDebugLoc(), TII.get(FCMPOpcode))
885 if (!constrainSelectedInstRegOperands(*FCMP, TII, TRI, RBI))
888 MachineInstr *Move = BuildMI(MBB, I, I.getDebugLoc(), TII.get(MoveOpcode))
893 if (!constrainSelectedInstRegOperands(*Move, TII, TRI, RBI))
900 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SYNC)).addImm(0);
909 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LEA_ADDiu))
913 if (!constrainSelectedInstRegOperands(*LEA_ADDiu, TII, TRI, RBI))
916 MachineInstr *Store = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SW))
920 if (!constrainSelectedInstRegOperands(*Store, TII, TRI, RBI))
931 return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);