• Home
  • History
  • Annotate
  • Raw
  • Download
  • only in /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/

Lines Matching defs:Src1Reg

1201       Register Src1Reg = MI.getOperand(1).getReg();
1203 Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1204 Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1225 Register Src1Reg = MI.getOperand(1).getReg();
1228 Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1229 Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
3325 unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
3340 Src1Reg = MI.getOperand(1).getReg();
3344 isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg))
3377 Src1Reg = MI.getOperand(1).getReg();
3381 isIntRegForSubInst(Src1Reg) && (MI.getOperand(2).getImm() == 0))
3392 Src1Reg = MI.getOperand(0).getReg();
3393 if (Hexagon::PredRegsRegClass.contains(Src1Reg) &&
3394 (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg))
3815 unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
3953 Src1Reg = MI.getOperand(0).getReg();
3955 if (Hexagon::IntRegsRegClass.contains(Src1Reg) &&
3957 HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
3961 if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3969 Src1Reg = MI.getOperand(0).getReg();
3971 if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3987 Src1Reg = MI.getOperand(0).getReg();
3989 if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3997 Src1Reg = MI.getOperand(0).getReg();
4000 Hexagon::IntRegsRegClass.contains(Src1Reg) &&
4001 HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
4008 Src1Reg = MI.getOperand(0).getReg();
4009 if (isIntRegForSubInst(Src1Reg) && MI.getOperand(1).isImm() &&
4017 Src1Reg = MI.getOperand(0).getReg();
4018 if (isIntRegForSubInst(Src1Reg) &&
4073 Src1Reg = MI.getOperand(1).getReg();
4075 if (isIntRegForSubInst(DstReg) && (DstReg == Src1Reg) &&