Lines Matching defs:RegisterRef
177 struct RegisterRef {
178 RegisterRef(const MachineOperand &Op) : Reg(Op.getReg()),
180 RegisterRef(unsigned R = 0, unsigned S = 0) : Reg(R), Sub(S) {}
182 bool operator== (RegisterRef RR) const {
185 bool operator!= (RegisterRef RR) const { return !operator==(RR); }
186 bool operator< (RegisterRef RR) const {
201 void addRefToMap(RegisterRef RR, ReferenceMap &Map, unsigned Exec);
202 bool isRefInMap(RegisterRef, ReferenceMap &Map, unsigned Exec);
220 MachineInstr *getReachingDefForPred(RegisterRef RD,
228 void renameInRange(RegisterRef RO, RegisterRef RN, unsigned PredR,
235 bool isIntReg(RegisterRef RR, unsigned &BW);
237 bool coalesceRegisters(RegisterRef R1, RegisterRef R2);
294 void HexagonExpandCondsets::addRefToMap(RegisterRef RR, ReferenceMap &Map,
304 bool HexagonExpandCondsets::isRefInMap(RegisterRef RR, ReferenceMap &Map,
469 std::set<RegisterRef> DefRegs;
496 std::map<RegisterRef,unsigned> ImpUses;
519 for (std::pair<RegisterRef, unsigned> P : ImpUses) {
520 RegisterRef R = P.first;
584 RegisterRef RS = SO;
644 if (RegisterRef(SrcOp) == RegisterRef(DstR, DstSR))
691 RegisterRef RT(ST);
692 if (RT == RegisterRef(SF)) {
745 MachineInstr *HexagonExpandCondsets::getReachingDefForPred(RegisterRef RD,
768 RegisterRef RR = Op;
802 RegisterRef RR = Op;
908 void HexagonExpandCondsets::renameInRange(RegisterRef RO, RegisterRef RN,
922 if (!Op.isReg() || RO != RegisterRef(Op))
957 RegisterRef RT(MS);
1002 RegisterRef RR = Op;
1033 RegisterRef RD = MD;
1081 if (RegisterRef(I->getOperand(0)) == RegisterRef(I->getOperand(2))) {
1094 bool HexagonExpandCondsets::isIntReg(RegisterRef RR, unsigned &BW) {
1122 bool HexagonExpandCondsets::coalesceRegisters(RegisterRef R1, RegisterRef R2) {
1202 RegisterRef RD = CI->getOperand(0);
1203 RegisterRef RP = CI->getOperand(1);
1225 RegisterRef RS = S1;
1228 Done = coalesceRegisters(RD, RegisterRef(S1));
1236 RegisterRef RS = S2;
1239 Done = coalesceRegisters(RD, RegisterRef(S2));