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  • only in /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/

Lines Matching refs:RegisterSubReg

85   struct RegisterSubReg {
88 explicit RegisterSubReg(unsigned R, unsigned SR = 0) : Reg(R), SubReg(SR) {}
89 explicit RegisterSubReg(const MachineOperand &MO)
96 bool operator== (const RegisterSubReg &R) const {
316 virtual bool evaluate(const RegisterSubReg &R, const LatticeCell &SrcC,
359 bool getCell(const RegisterSubReg &R, const CellMap &Inputs, LatticeCell &RC);
365 bool evaluateCMPrr(uint32_t Cmp, const RegisterSubReg &R1, const RegisterSubReg &R2,
367 bool evaluateCMPri(uint32_t Cmp, const RegisterSubReg &R1, const APInt &A2,
369 bool evaluateCMPrp(uint32_t Cmp, const RegisterSubReg &R1, uint64_t Props2,
378 bool evaluateCOPY(const RegisterSubReg &R1, const CellMap &Inputs,
382 bool evaluateANDrr(const RegisterSubReg &R1, const RegisterSubReg &R2,
384 bool evaluateANDri(const RegisterSubReg &R1, const APInt &A2,
387 bool evaluateORrr(const RegisterSubReg &R1, const RegisterSubReg &R2,
389 bool evaluateORri(const RegisterSubReg &R1, const APInt &A2,
392 bool evaluateXORrr(const RegisterSubReg &R1, const RegisterSubReg &R2,
394 bool evaluateXORri(const RegisterSubReg &R1, const APInt &A2,
399 bool evaluateZEXTr(const RegisterSubReg &R1, unsigned Width, unsigned Bits,
403 bool evaluateSEXTr(const RegisterSubReg &R1, unsigned Width, unsigned Bits,
409 bool evaluateCLBr(const RegisterSubReg &R1, bool Zeros, bool Ones,
412 bool evaluateCTBr(const RegisterSubReg &R1, bool Zeros, bool Ones,
417 bool evaluateEXTRACTr(const RegisterSubReg &R1, unsigned Width, unsigned Bits,
423 bool evaluateSplatr(const RegisterSubReg &R1, unsigned Bits, unsigned Count,
635 RegisterSubReg DefR(MD);
662 RegisterSubReg UseR(SO);
705 RegisterSubReg DefR(MO);
1087 bool MachineConstEvaluator::getCell(const RegisterSubReg &R, const CellMap &Inputs,
1113 bool MachineConstEvaluator::evaluateCMPrr(uint32_t Cmp, const RegisterSubReg &R1,
1114 const RegisterSubReg &R2, const CellMap &Inputs, bool &Result) {
1152 bool MachineConstEvaluator::evaluateCMPri(uint32_t Cmp, const RegisterSubReg &R1,
1179 bool MachineConstEvaluator::evaluateCMPrp(uint32_t Cmp, const RegisterSubReg &R1,
1372 bool MachineConstEvaluator::evaluateCOPY(const RegisterSubReg &R1,
1377 bool MachineConstEvaluator::evaluateANDrr(const RegisterSubReg &R1,
1378 const RegisterSubReg &R2, const CellMap &Inputs, LatticeCell &Result) {
1408 bool MachineConstEvaluator::evaluateANDri(const RegisterSubReg &R1,
1444 bool MachineConstEvaluator::evaluateORrr(const RegisterSubReg &R1,
1445 const RegisterSubReg &R2, const CellMap &Inputs, LatticeCell &Result) {
1475 bool MachineConstEvaluator::evaluateORri(const RegisterSubReg &R1,
1511 bool MachineConstEvaluator::evaluateXORrr(const RegisterSubReg &R1,
1512 const RegisterSubReg &R2, const CellMap &Inputs, LatticeCell &Result) {
1540 bool MachineConstEvaluator::evaluateXORri(const RegisterSubReg &R1,
1573 bool MachineConstEvaluator::evaluateZEXTr(const RegisterSubReg &R1, unsigned Width,
1604 bool MachineConstEvaluator::evaluateSEXTr(const RegisterSubReg &R1, unsigned Width,
1669 bool MachineConstEvaluator::evaluateCLBr(const RegisterSubReg &R1, bool Zeros,
1704 bool MachineConstEvaluator::evaluateCTBr(const RegisterSubReg &R1, bool Zeros,
1739 bool MachineConstEvaluator::evaluateEXTRACTr(const RegisterSubReg &R1,
1797 bool MachineConstEvaluator::evaluateSplatr(const RegisterSubReg &R1,
1854 bool evaluate(const RegisterSubReg &R, const LatticeCell &SrcC,
1869 bool evaluateHexRSEQ32(RegisterSubReg RL, RegisterSubReg RH, const CellMap &Inputs,
1943 RegisterSubReg DefR(MD);
1950 RegisterSubReg SrcR(MI.getOperand(1));
1972 RegisterSubReg SrcRL(OpLo), SrcRH(OpHi);
2059 RegisterSubReg R(MI.getOperand(1));
2099 RegisterSubReg R1(MI.getOperand(1));
2131 RegisterSubReg R1(MI.getOperand(1));
2159 RegisterSubReg R1(MI.getOperand(1));
2210 bool HexagonConstEvaluator::evaluate(const RegisterSubReg &R,
2301 RegisterSubReg PR(MD);
2523 bool HexagonConstEvaluator::evaluateHexRSEQ32(RegisterSubReg RL, RegisterSubReg RH,
2592 RegisterSubReg DefR(MI.getOperand(0));
2612 RegisterSubReg R1(Src1);
2614 RegisterSubReg R2(Src2);
2623 RegisterSubReg R2(Src2);
2642 RegisterSubReg R1(Src1);
2650 Eval = evaluateANDrr(R1, RegisterSubReg(Src2), Inputs, RC);
2661 Eval = evaluateORrr(R1, RegisterSubReg(Src2), Inputs, RC);
2672 Eval = evaluateXORrr(R1, RegisterSubReg(Src2), Inputs, RC);
2676 RegisterSubReg DefR(MI.getOperand(0));
2685 RegisterSubReg CR(MI.getOperand(1));
2700 RegisterSubReg DefR(MI.getOperand(0));
2713 RegisterSubReg R(ValOp);
2728 RegisterSubReg R1(MI.getOperand(1));
2758 RegisterSubReg DefR(MI.getOperand(0));
2772 RegisterSubReg DefR(MI.getOperand(0));
2773 RegisterSubReg R1(MI.getOperand(1));
2811 RegisterSubReg R(MO);
2982 RegisterSubReg DefR(MI.getOperand(0));
2984 RegisterSubReg R2(MI.getOperand(2));
2985 RegisterSubReg R3(MI.getOperand(3));
2999 RegisterSubReg R1(Acc);
3046 RegisterSubReg R1(MI.getOperand(1));
3047 RegisterSubReg R2(MI.getOperand(2));
3065 RegisterSubReg SR(SO);
3066 RegisterSubReg DefR(MI.getOperand(0));
3082 RegisterSubReg R1(MI.getOperand(1));
3083 RegisterSubReg R2(MI.getOperand(2));
3097 RegisterSubReg SR(SO);
3098 RegisterSubReg DefR(MI.getOperand(0));