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  • only in /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/

Lines Matching defs:R2

365     bool evaluateCMPrr(uint32_t Cmp, const RegisterSubReg &R1, const RegisterSubReg &R2,
382 bool evaluateANDrr(const RegisterSubReg &R1, const RegisterSubReg &R2,
387 bool evaluateORrr(const RegisterSubReg &R1, const RegisterSubReg &R2,
392 bool evaluateXORrr(const RegisterSubReg &R1, const RegisterSubReg &R2,
1114 const RegisterSubReg &R2, const CellMap &Inputs, bool &Result) {
1115 assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg));
1117 if (!getCell(R1, Inputs, LS1) || !getCell(R2, Inputs, LS2))
1127 return evaluateCMPrp(NegCmp, R2, Prop1, Inputs, Result);
1378 const RegisterSubReg &R2, const CellMap &Inputs, LatticeCell &Result) {
1379 assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg));
1380 const LatticeCell &L1 = Inputs.get(R2.Reg);
1381 const LatticeCell &L2 = Inputs.get(R2.Reg);
1388 return evaluateANDrr(R2, R1, Inputs, Result);
1391 if (!evaluate(R2, L2, LS2))
1445 const RegisterSubReg &R2, const CellMap &Inputs, LatticeCell &Result) {
1446 assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg));
1447 const LatticeCell &L1 = Inputs.get(R2.Reg);
1448 const LatticeCell &L2 = Inputs.get(R2.Reg);
1455 return evaluateORrr(R2, R1, Inputs, Result);
1458 if (!evaluate(R2, L2, LS2))
1512 const RegisterSubReg &R2, const CellMap &Inputs, LatticeCell &Result) {
1513 assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg));
1515 if (!getCell(R1, Inputs, LS1) || !getCell(R2, Inputs, LS2))
2614 RegisterSubReg R2(Src2);
2615 return evaluateCMPrr(Cmp, R1, R2, Inputs, Result);
2623 RegisterSubReg R2(Src2);
2625 return evaluateCMPri(NegCmp, R2, A1, Inputs, Result);
2978 // Convert DefR += mpyi(R2, R3)
2984 RegisterSubReg R2(MI.getOperand(2));
2986 assert(Inputs.has(R2.Reg) && Inputs.has(R3.Reg));
2990 bool HasC2 = getCell(R2, Inputs, LS2), HasC3 = getCell(R3, Inputs, LS3);
3047 RegisterSubReg R2(MI.getOperand(2));
3048 assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg));
3057 else if (getCell(R2, Inputs, LS2) && LS2.isSingle()) {
3083 RegisterSubReg R2(MI.getOperand(2));
3084 assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg));
3092 else if (getCell(R2, Inputs, LS2) && (LS2.properties() & P::Zero))