Lines Matching refs:ED
365 ExtValue(const ExtDesc &ED) : ExtValue(ED.getOp()) {}
395 OffsetRange getOffsetRange(const ExtDesc &ED) const;
406 bool replaceInstrExact(const ExtDesc &ED, Register ExtR);
407 bool replaceInstrExpr(const ExtDesc &ED, const ExtenderInit &ExtI,
426 friend raw_ostream &operator<< (raw_ostream &OS, const ExtDesc &ED);
493 raw_ostream &operator<< (raw_ostream &OS, const HCE::ExtDesc &ED) {
494 assert(ED.OpNum != -1u);
495 const MachineBasicBlock &MBB = *ED.getOp().getParent()->getParent();
499 if (ED.Rd.Reg != 0)
500 OS << printReg(ED.Rd.Reg, &HRI, ED.Rd.Sub);
503 OS << " = " << PrintExpr(ED.Expr, HRI);
504 if (ED.IsDef)
1093 // Return the allowable deviation from the current value of the extender ED,
1094 // for which the instruction corresponding to ED can be modified without
1100 OffsetRange HCE::getOffsetRange(const ExtDesc &ED) const {
1102 // the instruction using ED will be converted to an indexed memory
1104 unsigned IdxOpc = getRegOffOpcode(ED.UseMI->getOpcode());
1114 if (!ED.UseMI->mayLoad() && !ED.UseMI->mayStore())
1144 ExtDesc ED;
1145 ED.OpNum = OpNum;
1164 ED.Rd = MI.getOperand(OpNum-1);
1165 ED.IsDef = true;
1172 ED.Expr.Rs = MI.getOperand(OpNum-1);
1175 ED.Expr.Rs = MI.getOperand(OpNum-2);
1176 ED.Expr.S = MI.getOperand(OpNum-1).getImm();
1184 ED.Rd = MI.getOperand(0);
1185 ED.IsDef = true;
1189 ED.Rd = { MI.getOperand(0).getReg(), Hexagon::isub_hi };
1190 ED.IsDef = true;
1193 ED.Rd = { MI.getOperand(0).getReg(), Hexagon::isub_lo };
1194 ED.IsDef = true;
1197 ED.Rd = MI.getOperand(0);
1198 ED.Expr.Rs = MI.getOperand(OpNum-1);
1203 ED.Expr.Rs = MI.getOperand(OpNum-1);
1206 ED.Rd = MI.getOperand(0);
1207 ED.Expr.Rs = MI.getOperand(OpNum+1);
1208 ED.Expr.Neg = true;
1211 ED.Expr.Rs = MI.getOperand(OpNum+1);
1212 ED.Expr.Neg = true;
1219 ED.UseMI = &MI;
1222 ExtRoot ER(ED.getOp());
1226 Extenders.push_back(ED);
1275 const ExtDesc &ED = Extenders[I];
1276 if (!ED.IsDef)
1278 ExtValue EV(ED);
1279 LLVM_DEBUG(dbgs() << " =" << I << ". " << EV << " " << ED << '\n');
1280 assert(ED.Rd.Reg != 0);
1281 Ranges[I-Begin] = getOffsetRange(ED.Rd).shift(EV.Offset);
1286 if (ED.UseMI->getOpcode() == Hexagon::A2_tfrsi) {
1295 const ExtDesc &ED = Extenders[I];
1296 if (ED.IsDef)
1298 ExtValue EV(ED);
1299 LLVM_DEBUG(dbgs() << " " << I << ". " << EV << " " << ED << '\n');
1300 OffsetRange Dev = getOffsetRange(ED);
1465 const ExtDesc &ED = Extenders[I];
1466 return ED.Expr.Rs.isSlot() == IsStack &&
1467 ExtValue(ED).Offset == EV.Offset;
1495 const ExtDesc &ED = Extenders[Refs[i]];
1496 MachineBasicBlock *MBB = ED.UseMI->getParent();
1497 RefMIs.insert(ED.UseMI);
1603 bool HCE::replaceInstrExact(const ExtDesc &ED, Register ExtR) {
1604 MachineInstr &MI = *ED.UseMI;
1648 unsigned RegN = ED.OpNum;
1719 // Replace the extender ED with a form corresponding to the initializer ExtI.
1720 bool HCE::replaceInstrExpr(const ExtDesc &ED, const ExtenderInit &ExtI,
1722 MachineInstr &MI = *ED.UseMI;
1851 const ExtDesc &ED = Extenders[Idx];
1852 assert((!ED.IsDef || ED.Rd.Reg != 0) && "Missing Rd for def");
1854 assert(ExtRoot(ExtValue(ED)) == ExtRoot(DefV) && "Extender root mismatch");
1857 ExtValue EV(ED);
1859 const MachineInstr &MI = *ED.UseMI;
1873 // If ED is a def, and Diff is not 0, then all uses of the register Rd
1874 // defined by ED must be in the form (Rd, imm), i.e. the immediate offset
1877 if (ED.IsDef && Diff != 0) {
1878 for (MachineOperand &Op : MRI->use_operands(ED.Rd.Reg)) {
1887 Replaced = replaceInstrExact(ED, ExtR);
1889 Replaced = replaceInstrExpr(ED, ExtI, ExtR, Diff);
1891 if (Diff != 0 && Replaced && ED.IsDef) {
1905 assert(ED.Rd.Sub == 0 && ExtR.Sub == 0);
1906 MRI->replaceRegWith(ED.Rd.Reg, ExtR.Reg);