Lines Matching refs:RR
211 static bool getSubregMask(const BitTracker::RegisterRef &RR,
227 const BitTracker::RegisterRef &RR, MachineRegisterInfo &MRI);
405 bool HexagonBitSimplify::getSubregMask(const BitTracker::RegisterRef &RR,
407 const TargetRegisterClass *RC = MRI.getRegClass(RR.Reg);
408 if (RR.Sub == 0) {
420 if (RR.Sub == Hexagon::isub_hi || RR.Sub == Hexagon::vsub_hi)
896 const BitTracker::RegisterRef &RR, MachineRegisterInfo &MRI) {
897 if (!Register::isVirtualRegister(RR.Reg))
899 auto *RC = MRI.getRegClass(RR.Reg);
900 if (RR.Sub == 0)
913 VerifySR(RC, RR.Sub);
916 VerifySR(RC, RR.Sub);
1260 BitTracker::RegisterRef RR = MI.getOperand(OpN);
1261 const TargetRegisterClass *RC = HBS::getFinalVRegClass(RR, MRI);
2354 BitTracker::RegisterRef RR(V.RefI.Reg, 0);
2357 RR.Sub = Hexagon::isub_lo;
2360 RR.Sub = Hexagon::isub_hi;
2368 .addReg(RR.Reg, 0, RR.Sub)