Lines Matching refs:i16
40 addRegisterClass(MVT::i16, &AVR::DREGSRegClass);
51 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
52 setOperationAction(ISD::BlockAddress, MVT::i16, Custom);
57 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand);
66 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
85 setOperationAction(ISD::SRA, MVT::i16, Custom);
86 setOperationAction(ISD::SHL, MVT::i16, Custom);
87 setOperationAction(ISD::SRL, MVT::i16, Custom);
88 setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand);
89 setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand);
90 setOperationAction(ISD::SRL_PARTS, MVT::i16, Expand);
93 setOperationAction(ISD::ROTL, MVT::i16, Expand);
95 setOperationAction(ISD::ROTR, MVT::i16, Expand);
98 setOperationAction(ISD::BR_CC, MVT::i16, Custom);
104 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom);
108 setOperationAction(ISD::SETCC, MVT::i16, Custom);
112 setOperationAction(ISD::SELECT, MVT::i16, Expand);
114 setOperationAction(ISD::BSWAP, MVT::i16, Expand);
118 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
120 setIndexedLoadAction(ISD::PRE_DEC, MVT::i16, Legal);
122 setIndexedStoreAction(ISD::POST_INC, MVT::i16, Legal);
124 setIndexedStoreAction(ISD::PRE_DEC, MVT::i16, Legal);
146 setOperationAction(ISD::UDIV, MVT::i16, Expand);
148 setOperationAction(ISD::UREM, MVT::i16, Expand);
150 setOperationAction(ISD::SDIV, MVT::i16, Expand);
152 setOperationAction(ISD::SREM, MVT::i16, Expand);
156 setOperationAction(ISD::UDIVREM, MVT::i16, Custom);
159 setOperationAction(ISD::SDIVREM, MVT::i16, Custom);
164 setOperationAction(ISD::MUL, MVT::i16, Expand);
167 setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand);
168 setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand);
359 case MVT::i16:
537 SDValue LHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS,
539 SDValue LHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS,
541 SDValue RHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS,
543 SDValue RHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS,
561 SDValue LHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0,
563 SDValue LHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0,
565 SDValue LHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1,
567 SDValue LHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1,
575 SDValue RHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0,
577 SDValue RHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0,
579 SDValue RHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1,
581 SDValue RHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1,
595 } else if (VT == MVT::i8 || VT == MVT::i16) {
797 if (VT != MVT::i8 && VT != MVT::i16) {
810 if ((VT == MVT::i16 && RHSC != -2) || (VT == MVT::i8 && RHSC != -1)) {
848 if (VT != MVT::i8 && VT != MVT::i16) {
860 if ((VT == MVT::i16 && RHSC != 2) || (VT == MVT::i8 && RHSC != 1)) {
955 } else if (VT == MVT::i16) {
959 "calling convention can only manage i8 and i16 types");
1008 } else if (VT == MVT::i16) {
1011 llvm_unreachable("calling convention can only manage i8 and i16 types");
1049 } else if (RegVT == MVT::i16) {
1058 // :NOTE: Clang should not promote any i8 into i16 but for safety the
1817 // We only support i8 and i16.
1820 // assert((VT == MVT::i16 || VT == MVT::i8) && "Wrong operand type.");
1840 assert(VT == MVT::i16 && "inline asm constraint too large");
1924 // so we force it to i16 at least.
1926 Ty = MVT::i16;