Lines Matching refs:buildMI
64 MachineInstrBuilder buildMI(Block &MBB, BlockIt MBBI, unsigned Opcode) {
68 MachineInstrBuilder buildMI(Block &MBB, BlockIt MBBI, unsigned Opcode,
154 buildMI(MBB, MBBI, OpLo)
159 auto MIBHI = buildMI(MBB, MBBI, OpHi)
187 auto MIBLO = buildMI(MBB, MBBI, Op)
195 auto MIBHI = buildMI(MBB, MBBI, Op)
235 auto MIBLO = buildMI(MBB, MBBI, Op)
245 auto MIBHI = buildMI(MBB, MBBI, Op)
283 auto MIBLO = buildMI(MBB, MBBI, AVR::SUBIRdK)
287 auto MIBHI = buildMI(MBB, MBBI, AVR::SBCIRdK)
340 auto MIBLO = buildMI(MBB, MBBI, OpLo)
348 auto MIBHI = buildMI(MBB, MBBI, OpHi)
400 auto MIBLO = buildMI(MBB, MBBI, OpLo)
407 auto MIBHI = buildMI(MBB, MBBI, OpHi)
433 buildMI(MBB, MBBI, OpLo)
437 auto MIBHI = buildMI(MBB, MBBI, OpHi)
465 auto MIBLO = buildMI(MBB, MBBI, OpLo)
472 auto MIBHI = buildMI(MBB, MBBI, OpHi)
496 auto MIBLO = buildMI(MBB, MBBI, OpLo)
499 auto MIBHI = buildMI(MBB, MBBI, OpHi)
545 auto MIBLO = buildMI(MBB, MBBI, OpLo)
548 auto MIBHI = buildMI(MBB, MBBI, OpHi)
599 auto MIBLO = buildMI(MBB, MBBI, OpLo)
605 buildMI(MBB, MBBI, AVR::PUSHRr).addReg(TmpReg);
608 auto MIBHI = buildMI(MBB, MBBI, OpHi)
615 buildMI(MBB, MBBI, AVR::MOVRdRr).addReg(DstHiReg).addReg(TmpReg);
618 buildMI(MBB, MBBI, AVR::POPRd).addReg(DstLoReg);
642 auto MIBLO = buildMI(MBB, MBBI, OpLo)
647 auto MIBHI = buildMI(MBB, MBBI, OpHi)
673 auto MIBHI = buildMI(MBB, MBBI, OpHi)
678 auto MIBLO = buildMI(MBB, MBBI, OpLo)
715 auto MIBLO = buildMI(MBB, MBBI, OpLo)
722 buildMI(MBB, MBBI, AVR::PUSHRr).addReg(TmpReg);
725 auto MIBHI = buildMI(MBB, MBBI, OpHi)
732 buildMI(MBB, MBBI, AVR::MOVRdRr).addReg(DstHiReg).addReg(TmpReg);
735 buildMI(MBB, MBBI, AVR::POPRd).addReg(DstLoReg);
765 auto MIBLO = buildMI(MBB, MBBI, OpLo)
771 buildMI(MBB, MBBI, AVR::PUSHRr).addReg(TmpReg);
774 auto MIBHI = buildMI(MBB, MBBI, OpHi)
780 buildMI(MBB, MBBI, AVR::MOVRdRr).addReg(DstHiReg).addReg(TmpReg);
783 buildMI(MBB, MBBI, AVR::POPRd).addReg(DstLoReg);
804 buildMI(MBB, MBBI, AVR::INRdA)
809 buildMI(MBB, MBBI, AVR::BCLRs).addImm(7); // CLI
814 buildMI(MBB, MBBI, AVR::OUTARr)
832 *buildMI(MBB, MBBI, Opcode).add(Op1).add(Op2).getInstr();
855 buildMI(MBB, MBBI, LoadOpcode).add(Op1).add(Op2);
858 buildMI(MBB, MBBI, ArithOpcode).add(Op1).add(Op1).add(Op2);
861 buildMI(MBB, MBBI, StoreOpcode).add(Op2).add(Op1);
980 auto MIBHI = buildMI(MBB, MBBI, OpHi);
981 auto MIBLO = buildMI(MBB, MBBI, OpLo);
1026 auto MIBLO = buildMI(MBB, MBBI, OpLo)
1030 auto MIBHI = buildMI(MBB, MBBI, OpHi)
1057 auto MIBLO = buildMI(MBB, MBBI, OpLo)
1063 auto MIBHI = buildMI(MBB, MBBI, OpHi)
1091 auto MIBHI = buildMI(MBB, MBBI, OpHi)
1097 auto MIBLO = buildMI(MBB, MBBI, OpLo)
1127 auto MIBLO = buildMI(MBB, MBBI, OpLo)
1132 auto MIBHI = buildMI(MBB, MBBI, OpHi)
1159 auto MIBLO = buildMI(MBB, MBBI, OpLo)
1163 auto MIBHI = buildMI(MBB, MBBI, OpHi)
1190 auto MIBHI = buildMI(MBB, MBBI, OpHi)
1194 auto MIBLO = buildMI(MBB, MBBI, OpLo)
1217 buildMI(MBB, MBBI, OpLo)
1222 buildMI(MBB, MBBI, OpHi)
1240 buildMI(MBB, MBBI, OpHi, DstHiReg).setMIFlags(Flags); // High
1241 buildMI(MBB, MBBI, OpLo, DstLoReg).setMIFlags(Flags); // Low
1266 buildMI(MBB, MBBI, OpShift)
1272 auto MIB = buildMI(MBB, MBBI, OpCarry)
1307 buildMI(MBB, MBBI, OpShiftOut)
1312 buildMI(MBB, MBBI, OpLoad)
1317 buildMI(MBB, MBBI, OpShiftIn)
1322 auto MIB = buildMI(MBB, MBBI, OpAdd)
1347 buildMI(MBB, MBBI, OpLo)
1352 auto MIBHI = buildMI(MBB, MBBI, OpHi)
1380 buildMI(MBB, MBBI, OpHi)
1384 auto MIBLO = buildMI(MBB, MBBI, OpLo)
1423 buildMI(MBB, MBBI, OpHi)
1427 auto MIBLO = buildMI(MBB, MBBI, OpLo)
1465 auto MOV = buildMI(MBB, MBBI, AVR::MOVRdRr)
1475 buildMI(MBB, MBBI, AVR::MOVRdRr)
1480 buildMI(MBB, MBBI, AVR::ADDRdRr) // LSL Rd <==> ADD Rd, Rr
1485 auto SBC = buildMI(MBB, MBBI, AVR::SBCRdRr)
1519 buildMI(MBB, MBBI, AVR::MOVRdRr)
1524 auto EOR = buildMI(MBB, MBBI, AVR::EORRdRr)
1548 buildMI(MBB, MBBI, OpLo)
1554 buildMI(MBB, MBBI, OpHi)
1572 buildMI(MBB, MBBI, AVR::INRdA)
1577 buildMI(MBB, MBBI, AVR::BCLRs).addImm(0x07).setMIFlags(Flags);
1579 buildMI(MBB, MBBI, AVR::OUTARr)
1584 buildMI(MBB, MBBI, AVR::OUTARr)
1589 buildMI(MBB, MBBI, AVR::OUTARr)