Lines Matching refs:R4
221 case ARM::R4:
286 case ARM::R4:
408 // Emit the following sequence, using R4 as a temporary, since we cannot use
414 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)
418 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSRri), ARM::R4)
420 .addReg(ARM::R4, RegState::Kill)
424 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSLri), ARM::R4)
426 .addReg(ARM::R4, RegState::Kill)
431 .addReg(ARM::R4, RegState::Kill)
517 assert(!MFI.getPristineRegs(MF).test(ARM::R4) &&
519 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
522 .addReg(ARM::R4)
853 for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::LR}) {
875 ARM::R5, ARM::R4, ARM::R3,
983 ARM::R4, ARM::R5, ARM::R6, ARM::R7};