Lines Matching refs:MCInst
26 #include "llvm/MC/MCInst.h"
80 uint64_t getBinaryCodeForInstr(const MCInst &MI,
86 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
93 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
97 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
104 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
110 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
115 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
120 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
125 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
131 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
137 uint32_t getThumbBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
143 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
146 uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
149 uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
155 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
158 uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
161 uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
165 uint32_t getITMaskOpValue(const MCInst &MI, unsigned OpIdx,
171 uint32_t getMVEShiftImmOpValue(const MCInst &MI, unsigned OpIdx,
177 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
182 uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
188 uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
194 uint32_t getT2AddrModeImm7s4OpValue(const MCInst &MI, unsigned OpIdx,
200 uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
207 uint32_t getT2ScaledImmOpValue(const MCInst &MI, unsigned OpIdx,
213 uint32_t getMveAddrModeRQOpValue(const MCInst &MI, unsigned OpIdx,
220 uint32_t getMveAddrModeQOpValue(const MCInst &MI, unsigned OpIdx,
226 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
231 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
260 uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
265 uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
270 uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
275 uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
281 uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
286 uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
291 uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
296 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
301 uint32_t getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,
306 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
314 unsigned getModImmOpValue(const MCInst &MI, unsigned Op,
333 unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
352 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
356 unsigned getT2AddrModeImmOpValue(const MCInst &MI, unsigned OpNum,
359 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
364 unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op,
367 unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op,
370 unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
374 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
380 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
384 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
387 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
390 unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
393 unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
396 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
400 unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
403 unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
406 unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
409 unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
413 unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op,
417 unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
420 unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
423 unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
426 unsigned NEONThumb2V8PostEncoder(const MCInst &MI,
430 unsigned VFPThumb2PostEncoder(const MCInst &MI,
434 uint32_t getPowerTwoOpValue(const MCInst &MI, unsigned OpIdx,
450 void encodeInstruction(const MCInst &MI, raw_ostream &OS,
455 uint32_t getBFTargetOpValue(const MCInst &MI, unsigned OpIdx,
459 uint32_t getBFAfterTargetOpValue(const MCInst &MI, unsigned OpIdx,
463 uint32_t getVPTMaskOpValue(const MCInst &MI, unsigned OpIdx,
466 uint32_t getRestrictedCondCodeOpValue(const MCInst &MI, unsigned OpIdx,
470 uint32_t getMVEPairVectorIndexOpValue(const MCInst &MI, unsigned OpIdx,
480 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
500 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
514 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
527 unsigned ARMMCCodeEmitter::NEONThumb2V8PostEncoder(const MCInst &MI,
540 VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue,
552 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
589 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
618 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
656 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
669 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
681 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
693 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
705 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
715 static bool HasConditionalBranch(const MCInst &MI) {
734 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
748 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
764 getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
779 getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
792 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
821 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
862 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
882 getITMaskOpValue(const MCInst &MI, unsigned OpIdx,
909 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
922 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
938 ARMMCCodeEmitter::getMVEShiftImmOpValue(const MCInst &MI, unsigned OpIdx,
972 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
1023 getT2ScaledImmOpValue(const MCInst &MI, unsigned OpIdx,
1054 getMveAddrModeRQOpValue(const MCInst &MI, unsigned OpIdx,
1074 getMveAddrModeQOpValue(const MCInst &MI, unsigned OpIdx,
1105 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
1146 ARMMCCodeEmitter::getT2AddrModeImm7s4OpValue(const MCInst &MI, unsigned OpIdx,
1173 getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
1186 ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
1242 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
1276 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1299 getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
1311 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1331 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
1368 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
1384 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
1399 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
1410 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
1450 getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,
1489 getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
1537 getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,
1584 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
1604 getT2AddrModeImmOpValue(const MCInst &MI, unsigned OpNum,
1629 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
1646 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
1689 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
1703 getRegisterListOpValue(const MCInst &MI, unsigned Op,
1750 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1774 getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
1801 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1822 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1831 getShiftRight8Imm(const MCInst &MI, unsigned Op,
1838 getShiftRight16Imm(const MCInst &MI, unsigned Op,
1845 getShiftRight32Imm(const MCInst &MI, unsigned Op,
1852 getShiftRight64Imm(const MCInst &MI, unsigned Op,
1859 encodeInstruction(const MCInst &MI, raw_ostream &OS,
1887 ARMMCCodeEmitter::getBFTargetOpValue(const MCInst &MI, unsigned OpIdx,
1897 ARMMCCodeEmitter::getBFAfterTargetOpValue(const MCInst &MI, unsigned OpIdx,
1919 uint32_t ARMMCCodeEmitter::getVPTMaskOpValue(const MCInst &MI, unsigned OpIdx,
1951 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
1979 getPowerTwoOpValue(const MCInst &MI, unsigned OpIdx,
1989 getMVEPairVectorIndexOpValue(const MCInst &MI, unsigned OpIdx,