Lines Matching refs:lsl
625 return parsePKHImm(O, "lsl", 0, 31);
1673 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1689 // Only lsl #{0, 1, 2, 3} allowed.
1692 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
3870 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
4016 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
4030 .Case("asl", ARM_AM::lsl)
4031 .Case("lsl", ARM_AM::lsl)
4078 // lsl, ror: 0 <= imm <= 31
4082 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
4087 // shift by zero is a nop. Always send it through as lsl.
4090 ShiftTy = ARM_AM::lsl;
5193 /// lsl #n 'n' in [0,31]
5202 Error(S, "shift operator 'asr' or 'lsl' expected");
5207 if (ShiftName == "lsl" || ShiftName == "LSL")
5212 Error(S, "shift operator 'asr' or 'lsl' expected");
5907 /// ( lsl | lsr | asr | ror ) , # shift_amount
5918 if (ShiftName == "lsl" || ShiftName == "LSL" ||
5920 St = ARM_AM::lsl;
5950 // lsl, ror: 0 <= imm <= 31
5957 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
5962 St = ARM_AM::lsl;
6439 Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
6546 Mnemonic == "eor" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
9853 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
9888 if (Shift == ARM_AM::lsl && Amount == 0) {
9903 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
9935 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
9960 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;