Lines Matching defs:MIB
1153 MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(),
1155 MIB.add(MI->getOperand(0));
1156 MIB.addImm(0);
1157 MIB.addImm(ARMCC::AL);
1158 MIB.addReg(ARM::NoRegister);
1164 MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(BrOpc));
1165 MIB.add(MI->getOperand(1)); // branch target
1166 MIB.addImm(ARMCC::EQ); // condition code
1167 MIB.addReg(ARM::CPSR);
1185 MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(),
1187 MIB.addDef(ARM::LR);
1188 MIB.add(MI->getOperand(1));
1189 MIB.add(MI->getOperand(2));
1190 MIB.addImm(ARMCC::AL);
1191 MIB.addReg(0);
1194 MIB.addReg(ARM::CPSR);
1195 MIB->getOperand(5).setIsDef(true);
1197 MIB.addReg(0);
1210 MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(),
1212 MIB.addReg(ARM::LR);
1213 MIB.addImm(0);
1214 MIB.addImm(ARMCC::AL);
1215 MIB.addReg(ARM::NoRegister);
1223 MachineInstrBuilder MIB =
1225 MIB.add(MI->getOperand(1)); // branch target
1226 MIB.addImm(ARMCC::NE); // condition code
1227 MIB.addReg(ARM::CPSR);
1334 MachineInstrBuilder MIB =
1337 MIB.addDef(ARM::LR);
1338 MIB.add(Count);
1340 MIB.add(Start->getOperand(1));
1346 LLVM_DEBUG(dbgs() << "ARM Loops: Inserted start: " << *MIB);
1347 return &*MIB;
1354 MachineInstrBuilder MIB =
1356 MIB.addDef(To);
1357 MIB.addReg(From);
1358 MIB.addReg(From);
1359 MIB.addImm(0);
1360 MIB.addReg(0);
1361 MIB.addReg(To);
1362 LLVM_DEBUG(dbgs() << "ARM Loops: Inserted VMOV: " << *MIB);
1457 MachineInstrBuilder MIB = BuildMI(*InsertAt->getParent(), InsertAt,
1460 MIB.addImm(0);
1462 LLVM_DEBUG(dbgs() << "ARM Loops: Created VPST: " << *MIB);
1464 LoLoop.BlockMasksToRecompute.insert(MIB.getInstr());
1518 MachineInstrBuilder MIB = BuildMI(*MBB, End, End->getDebugLoc(),
1520 MIB.addDef(ARM::LR);
1521 MIB.add(End->getOperand(0));
1522 MIB.add(End->getOperand(1));
1523 LLVM_DEBUG(dbgs() << "ARM Loops: Inserted LE: " << *MIB);
1526 return &*MIB;