Lines Matching defs:DL
171 MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
177 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
183 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
485 const DebugLoc &DL, unsigned Base,
552 BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBi8), Base)
573 BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBi8), Base)
628 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
743 BuildMI(MBB, InsertBefore, DL, TII->get(ARM::tMOVSr), NewBase)
746 BuildMI(MBB, InsertBefore, DL, TII->get(ARM::tMOVr), NewBase)
756 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase)
761 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase)
767 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase)
806 MIB = BuildMI(MBB, InsertBefore, DL, TII->get(Opcode));
815 UpdateBaseRegUses(MBB, InsertBefore, DL, Base, NumRegs, Pred, PredReg);
818 MIB = BuildMI(MBB, InsertBefore, DL, TII->get(Opcode));
835 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
843 MachineInstrBuilder MIB = BuildMI(MBB, InsertBefore, DL,
907 DebugLoc DL = First->getDebugLoc();
911 Opcode, Pred, PredReg, DL, Regs,
915 Opcode, Pred, PredReg, DL, Regs, Cand.Instrs);
1278 DebugLoc DL = MI->getDebugLoc();
1326 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc))
1434 DebugLoc DL = MI->getDebugLoc();
1482 BuildMI(MBB, MBBI, DL, TII->get(NewOpc))
1493 BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg())
1499 BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg())
1509 BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg())
1524 BuildMI(MBB, MBBI, DL, TII->get(NewOpc), Base)
1533 BuildMI(MBB, MBBI, DL, TII->get(NewOpc), Base)
1581 DebugLoc DL = MI.getDebugLoc();
1582 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc));