Lines Matching refs:SDValue
339 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
343 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
366 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
367 SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const;
368 SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const;
369 SDValue PerformIntrinsicCombine(SDNode *N, DAGCombinerInfo &DCI) const;
370 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
372 bool SimplifyDemandedBitsForTargetNode(SDValue Op,
394 bool isZExtFree(SDValue Val, EVT VT2) const override;
401 bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
440 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
447 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
448 SDValue &Offset, ISD::MemIndexedMode &AM,
451 void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
456 bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits,
479 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
480 std::vector<SDValue> &Ops,
704 std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const;
706 using RegsToPassVector = SmallVector<std::pair<unsigned, SDValue>, 8>;
708 void PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG, SDValue Chain,
709 SDValue &Arg, RegsToPassVector &RegsToPass,
711 SDValue &StackPtr,
712 SmallVectorImpl<SDValue> &MemOpChains,
714 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
715 SDValue &Root, SelectionDAG &DAG,
722 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
726 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
727 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
728 SDValue LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
729 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG,
731 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
733 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
734 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
735 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
736 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
737 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
738 SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const;
739 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
740 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
742 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
745 SDValue LowerGlobalTLSAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
746 SDValue LowerGlobalTLSAddressWindows(SDValue Op, SelectionDAG &DAG) const;
747 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
748 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
749 SDValue LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const;
750 SDValue LowerUnsignedALUO(SDValue Op, SelectionDAG &DAG) const;
751 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
752 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
753 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
754 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
755 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
756 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
757 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
758 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
759 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
760 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
761 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
763 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
765 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
766 SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
767 SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
768 SDValue LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed) const;
769 void ExpandDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed,
770 SmallVectorImpl<SDValue> &Results) const;
771 SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG,
773 SDValue LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG, bool Signed,
774 SDValue &Chain) const;
775 SDValue LowerREM(SDNode *N, SelectionDAG &DAG) const;
776 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
777 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
778 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
779 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
780 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
781 SDValue LowerFSETCC(SDValue Op, SelectionDAG &DAG) const;
782 void lowerABS(SDNode *N, SmallVectorImpl<SDValue> &Results,
784 void LowerLOAD(SDNode *N, SmallVectorImpl<SDValue> &Results,
790 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
796 SDValue MoveToHPR(const SDLoc &dl, SelectionDAG &DAG, MVT LocVT, MVT ValVT,
797 SDValue Val) const;
798 SDValue MoveFromHPR(const SDLoc &dl, SelectionDAG &DAG, MVT LocVT,
799 MVT ValVT, SDValue Val) const;
801 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
803 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
807 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
808 SDValue ThisVal) const;
821 splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val,
822 SDValue *Parts, unsigned NumParts, MVT PartVT,
825 SDValue
827 const SDValue *Parts, unsigned NumParts,
831 SDValue
832 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
835 SmallVectorImpl<SDValue> &InVals) const override;
838 SDValue &Chain, const Value *OrigArg,
843 const SDLoc &dl, SDValue &Chain,
847 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
848 SmallVectorImpl<SDValue> &InVals) const override;
857 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
860 const SmallVectorImpl<SDValue> &OutVals,
869 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
871 const SmallVectorImpl<SDValue> &OutVals,
874 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
882 SDValue getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal, SDValue TrueVal,
883 SDValue ARMcc, SDValue CCR, SDValue Cmp,
885 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
886 SDValue &ARMcc, SelectionDAG &DAG, const SDLoc &dl) const;
887 SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
889 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
891 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;