Lines Matching refs:MIB
10143 MachineInstrBuilder MIB;
10144 MIB = BuildMI(DispatchBB, dl, TII->get(ARM::Int_eh_sjlj_dispatchsetup));
10153 MIB.addRegMask(RI.getSjLjDispatchPreservedMask(*MF));
10431 MachineInstrBuilder MIB(*MF, &*II);
10444 MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead);
10794 MachineInstrBuilder MIB =
10797 MIB.addReg(varPhi)
10801 MIB->getOperand(5).setReg(ARM::CPSR);
10802 MIB->getOperand(5).setIsDef(true);
11051 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc));
11053 MIB.add(MI.getOperand(i));
11279 MachineInstrBuilder MIB(*MF, MI);
11293 MIB.addReg(TmpReg, RegState::Define|RegState::Dead);