Lines Matching defs:CondCode
470 const ISD::CondCode Cond;
546 const ISD::CondCode Cond;
643 const ISD::CondCode Cond;
1912 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
1929 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
1935 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
1937 case ISD::SETOGT: CondCode = ARMCC::GT; break;
1939 case ISD::SETOGE: CondCode = ARMCC::GE; break;
1940 case ISD::SETOLT: CondCode = ARMCC::MI; break;
1941 case ISD::SETOLE: CondCode = ARMCC::LS; break;
1942 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
1943 case ISD::SETO: CondCode = ARMCC::VC; break;
1944 case ISD::SETUO: CondCode = ARMCC::VS; break;
1945 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
1946 case ISD::SETUGT: CondCode = ARMCC::HI; break;
1947 case ISD::SETUGE: CondCode = ARMCC::PL; break;
1949 case ISD::SETULT: CondCode = ARMCC::LT; break;
1951 case ISD::SETULE: CondCode = ARMCC::LE; break;
1953 case ISD::SETUNE: CondCode = ARMCC::NE; break;
3899 DAG.getSetCC(dl, MVT::i1, CLSHi, Constant31, ISD::CondCode::SETEQ);
3901 DAG.getSetCC(dl, MVT::i1, Hi, Constant0, ISD::CondCode::SETEQ);
4462 SDValue ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
4570 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
4576 switch (CondCode) {
4579 CondCode = ARMCC::PL;
4582 CondCode = ARMCC::MI;
4588 switch (CondCode) {
4598 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
4894 static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
4900 CondCode = ARMCC::GE;
4905 CondCode = ARMCC::GT;
4925 CondCode = CondCode == ARMCC::GT ? ARMCC::GE : ARMCC::GT;
4931 CondCode = ARMCC::VS;
4939 CondCode = ARMCC::EQ;
4970 static bool isGTorGE(ISD::CondCode CC) {
4974 static bool isLTorLE(ISD::CondCode CC) {
4986 const ISD::CondCode CC, const SDValue K) {
4996 const ISD::CondCode CC, const SDValue K) {
5026 ISD::CondCode CC1 = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5036 ISD::CondCode CC2 = cast<CondCodeSDNode>(Op2.getOperand(4))->get();
5124 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5202 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5284 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
5285 if (CondCode == ARMCC::LT || CondCode == ARMCC::LE ||
5286 CondCode == ARMCC::VC || CondCode == ARMCC::NE) {
5301 ARMCC::CondCodes CondCode, CondCode2;
5302 FPCCToARMCC(CC, CondCode, CondCode2);
5315 checkVSELConstraints(CC, CondCode, swpCmpOps, swpVselOps);
5317 if (CondCode == ARMCC::GT || CondCode == ARMCC::GE ||
5318 CondCode == ARMCC::VS || CondCode == ARMCC::EQ) {
5326 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5408 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
5446 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
5447 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5480 ARMCC::CondCodes CondCode =
5482 CondCode = ARMCC::getOppositeCondition(CondCode);
5483 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
5495 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
5533 ARMCC::CondCodes CondCode =
5535 CondCode = ARMCC::getOppositeCondition(CondCode);
5536 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
5559 ARMCC::CondCodes CondCode, CondCode2;
5560 FPCCToARMCC(CC, CondCode, CondCode2);
5562 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
6415 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
9678 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(3))->get();
9695 ARMCC::CondCodes CondCode, CondCode2;
9696 FPCCToARMCC(CC, CondCode, CondCode2);
9705 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
15511 static SDValue SearchLoopIntrinsic(SDValue N, ISD::CondCode &CC, int &Imm,
15563 ISD::CondCode CC;
15594 auto IsTrueIfZero = [](ISD::CondCode CC, int Imm) {
15601 auto IsFalseIfZero = [](ISD::CondCode CC, int Imm) {