Lines Matching refs:NumAlignedDPRCS2Regs
76 unsigned NumAlignedDPRCS2Regs);
978 unsigned NumAlignedDPRCS2Regs,
997 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
1056 unsigned NumAlignedDPRCS2Regs) const {
1089 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
1165 /// Emit aligned spill instructions for NumAlignedDPRCS2Regs D-registers
1170 unsigned NumAlignedDPRCS2Regs,
1184 if (DNum > NumAlignedDPRCS2Regs - 1)
1217 .addImm(8 * NumAlignedDPRCS2Regs)
1240 // Now spill NumAlignedDPRCS2Regs registers starting from d8.
1246 if (NumAlignedDPRCS2Regs >= 6) {
1257 NumAlignedDPRCS2Regs -= 4;
1265 if (NumAlignedDPRCS2Regs >= 4) {
1276 NumAlignedDPRCS2Regs -= 4;
1280 if (NumAlignedDPRCS2Regs >= 2) {
1290 NumAlignedDPRCS2Regs -= 2;
1294 if (NumAlignedDPRCS2Regs) {
1312 unsigned NumAlignedDPRCS2Regs) {
1320 switch(NumAlignedDPRCS2Regs) {
1338 /// Emit aligned reload instructions for NumAlignedDPRCS2Regs D-registers
1343 unsigned NumAlignedDPRCS2Regs,
1374 // Now restore NumAlignedDPRCS2Regs registers starting from d8.
1378 if (NumAlignedDPRCS2Regs >= 6) {
1388 NumAlignedDPRCS2Regs -= 4;
1396 if (NumAlignedDPRCS2Regs >= 4) {
1405 NumAlignedDPRCS2Regs -= 4;
1409 if (NumAlignedDPRCS2Regs >= 2) {
1417 NumAlignedDPRCS2Regs -= 2;
1421 if (NumAlignedDPRCS2Regs)
1444 unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs();
1460 NumAlignedDPRCS2Regs, MachineInstr::FrameSetup);
1465 if (NumAlignedDPRCS2Regs)
1466 emitAlignedDPRCS2Spills(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
1480 unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs();
1484 if (NumAlignedDPRCS2Regs)
1485 emitAlignedDPRCS2Restores(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
1491 NumAlignedDPRCS2Regs);