Lines Matching defs:MIB
802 MachineInstrBuilder MIB =
808 MIB.addImm(0x800);
810 MIB.add(predOps(ARMCC::AL))
822 MachineInstrBuilder MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
825 MIB.addImm(0x800);
827 MIB.addImm(8);
829 MIB.addReg(SrcReg, getKillRegState(KillSrc))
834 void llvm::addUnpredicatedMveVpredNOp(MachineInstrBuilder &MIB) {
835 MIB.addImm(ARMVCC::None);
836 MIB.addReg(0);
839 void llvm::addUnpredicatedMveVpredROp(MachineInstrBuilder &MIB,
841 addUnpredicatedMveVpredNOp(MIB);
842 MIB.addReg(DestReg, RegState::Undef);
845 void llvm::addPredicatedMveVpredNOp(MachineInstrBuilder &MIB, unsigned Cond) {
846 MIB.addImm(Cond);
847 MIB.addReg(ARM::VPR, RegState::Implicit);
850 void llvm::addPredicatedMveVpredROp(MachineInstrBuilder &MIB,
852 addPredicatedMveVpredNOp(MIB, Cond);
853 MIB.addReg(Inactive);
887 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
888 MIB.addReg(SrcReg, getKillRegState(KillSrc));
890 MIB.addReg(SrcReg, getKillRegState(KillSrc));
892 addUnpredicatedMveVpredROp(MIB, DestReg);
894 MIB.add(predOps(ARMCC::AL));
1069 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
1073 return MIB.addReg(Reg, State);
1076 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
1077 return MIB.addReg(Reg, State, SubIdx);
1140 MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::STRD));
1141 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
1142 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
1143 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)
1148 MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::STMIA))
1152 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
1153 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
1177 auto MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::MVE_VSTRWU32));
1178 MIB.addReg(SrcReg, getKillRegState(isKill))
1182 addUnpredicatedMveVpredNOp(MIB);
1198 MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(),
1203 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
1204 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
1205 AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
1223 MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(),
1228 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
1229 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
1230 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
1231 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
1238 MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::VSTMDIA))
1242 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
1243 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
1244 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
1245 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
1246 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
1247 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
1248 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
1249 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
1376 MachineInstrBuilder MIB;
1379 MIB = BuildMI(MBB, I, DL, get(ARM::LDRD));
1380 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1381 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1382 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)
1387 MIB = BuildMI(MBB, I, DL, get(ARM::LDMIA))
1391 MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1392 MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1396 MIB.addReg(DestReg, RegState::ImplicitDefine);
1416 auto MIB = BuildMI(MBB, I, DL, get(ARM::MVE_VLDRWU32), DestReg);
1417 MIB.addFrameIndex(FI)
1420 addUnpredicatedMveVpredNOp(MIB);
1434 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1438 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1439 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1440 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1442 MIB.addReg(DestReg, RegState::ImplicitDefine);
1457 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1461 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1462 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1463 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1464 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1466 MIB.addReg(DestReg, RegState::ImplicitDefine);
1473 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1477 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1478 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1479 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1480 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1481 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI);
1482 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI);
1483 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI);
1484 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI);
1486 MIB.addReg(DestReg, RegState::ImplicitDefine);
1668 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
1680 MIB.add(predOps(ARMCC::AL));
1687 MIB.addReg(SrcRegS, RegState::Implicit);
2570 MachineInstrBuilder MIB(MF, &*MI);
2572 MIB.add(RegList[i]);
4835 MachineInstrBuilder MIB;
4841 MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg);
4842 MIB.addReg(Reg, RegState::Kill).addImm(0);
4848 MIB.addMemOperand(MMO).add(predOps(ARMCC::AL));
4851 MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg);
4852 MIB.addReg(Reg, RegState::Kill)
4989 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
5014 MIB.addReg(DstReg, RegState::Define)
5037 MIB.addReg(DstReg, RegState::Define)
5044 MIB.addReg(SrcReg, RegState::Implicit);
5067 MIB.addReg(DReg, RegState::Define)
5075 MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
5077 MIB.addReg(ImplicitSReg, RegState::Implicit);
5103 MIB.addReg(DDst, RegState::Define)
5110 MIB.addReg(DstReg, RegState::Implicit | RegState::Define);
5111 MIB.addReg(SrcReg, RegState::Implicit);
5113 MIB.addReg(ImplicitSReg, RegState::Implicit);
5150 MIB.addReg(DDst, RegState::Define);
5156 MIB.addReg(CurReg, getUndefRegState(CurUndef));
5160 MIB.addReg(CurReg, getUndefRegState(CurUndef))
5165 MIB.addReg(SrcReg, RegState::Implicit);
5169 MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
5171 MIB.addReg(ImplicitSReg, RegState::Implicit);
5982 MachineInstrBuilder MIB = BuildMI(MBB, MBB.end(), DebugLoc(), get(Opc))
5985 MIB.add(predOps(ARMCC::AL));
5999 MachineInstrBuilder MIB;
6010 MIB = BuildMI(MF, DebugLoc(), get(Opc))
6013 MIB.add(predOps(ARMCC::AL));
6014 It = MBB.insert(It, MIB);