Lines Matching defs:ARMBaseInstrInfo
1 //===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
13 #include "ARMBaseInstrInfo.h"
110 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
124 ARMBaseInstrInfo::CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
134 ScheduleHazardRecognizer *ARMBaseInstrInfo::
142 MachineInstr *ARMBaseInstrInfo::convertToThreeAddress(
312 bool ARMBaseInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
402 unsigned ARMBaseInstrInfo::removeBranch(MachineBasicBlock &MBB,
429 unsigned ARMBaseInstrInfo::insertBranch(MachineBasicBlock &MBB,
476 bool ARMBaseInstrInfo::
483 bool ARMBaseInstrInfo::isPredicated(const MachineInstr &MI) const {
499 std::string ARMBaseInstrInfo::createMIROperandComment(
524 bool ARMBaseInstrInfo::PredicateInstruction(
545 bool ARMBaseInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
571 bool ARMBaseInstrInfo::DefinesPredicate(
586 bool ARMBaseInstrInfo::isCPSRDefined(const MachineInstr &MI) {
593 bool ARMBaseInstrInfo::isAddrMode3OpImm(const MachineInstr &MI,
601 bool ARMBaseInstrInfo::isAddrMode3OpMinusReg(const MachineInstr &MI,
613 bool ARMBaseInstrInfo::isLdstScaledReg(const MachineInstr &MI,
621 bool ARMBaseInstrInfo::isLdstScaledRegNotPlusLsl2(const MachineInstr &MI,
635 bool ARMBaseInstrInfo::isLdstSoMinusReg(const MachineInstr &MI,
642 bool ARMBaseInstrInfo::isAm2ScaledReg(const MachineInstr &MI,
673 return !ARMBaseInstrInfo::isCPSRDefined(*MI);
680 bool ARMBaseInstrInfo::isPredicable(const MachineInstr &MI) const {
726 unsigned ARMBaseInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
783 unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr &MI) const {
794 void ARMBaseInstrInfo::copyFromCPSR(MachineBasicBlock &MBB,
814 void ARMBaseInstrInfo::copyToCPSR(MachineBasicBlock &MBB,
856 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
1023 ARMBaseInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
1039 ARMBaseInstrInfo::describeLoadedValue(const MachineInstr &MI,
1069 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
1080 void ARMBaseInstrInfo::
1258 unsigned ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
1308 unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
1321 void ARMBaseInstrInfo::
1495 unsigned ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
1551 unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
1566 void ARMBaseInstrInfo::expandMEMCPY(MachineBasicBlock::iterator MI) const {
1569 const ARMBaseInstrInfo *TII = Subtarget.getInstrInfo();
1620 bool ARMBaseInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
1745 void ARMBaseInstrInfo::reMaterialize(MachineBasicBlock &MBB,
1773 ARMBaseInstrInfo::duplicate(MachineBasicBlock &MBB,
1797 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr &MI0,
1891 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1972 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
2002 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
2049 bool ARMBaseInstrInfo::
2075 bool ARMBaseInstrInfo::
2140 ARMBaseInstrInfo::extraSizeToPredicateInstructions(const MachineFunction &MF,
2149 ARMBaseInstrInfo::predictBranchSizeForIfCvt(MachineInstr &MI) const {
2172 ARMBaseInstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,
2205 MachineInstr *ARMBaseInstrInfo::commuteInstructionImpl(MachineInstr &MI,
2234 ARMBaseInstrInfo::canFoldIntoMOVCC(Register Reg, const MachineRegisterInfo &MRI,
2269 bool ARMBaseInstrInfo::analyzeSelect(const MachineInstr &MI,
2291 ARMBaseInstrInfo::optimizeSelect(MachineInstr &MI,
2419 const ARMBaseInstrInfo &TII,
2579 const ARMBaseInstrInfo &TII) {
2734 bool ARMBaseInstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
2941 bool ARMBaseInstrInfo::optimizeCompareInstr(
3221 bool ARMBaseInstrInfo::shouldSink(const MachineInstr &MI) const {
3239 bool ARMBaseInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
3635 unsigned ARMBaseInstrInfo::getNumLDMAddresses(const MachineInstr &MI) const {
3689 unsigned ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
3803 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
3843 bool ARMBaseInstrInfo::isLDMBaseRegInList(const MachineInstr &MI) const {
3853 ARMBaseInstrInfo::getLDMVariableDefsSize(const MachineInstr &MI) const {
3860 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
3895 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
3935 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
3964 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
4308 int ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
4344 int ARMBaseInstrInfo::getOperandLatencyImpl(
4405 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
4663 unsigned ARMBaseInstrInfo::getPredicationCost(const MachineInstr &MI) const {
4682 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
4733 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
4751 bool ARMBaseInstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,
4772 bool ARMBaseInstrInfo::hasLowDefLatency(const TargetSchedModel &SchedModel,
4788 bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr &MI,
4824 void ARMBaseInstrInfo::expandLoadStackGuardBase(MachineBasicBlock::iterator MI,
4859 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
4895 ARMBaseInstrInfo::getExecutionDomain(const MachineInstr &MI) const {
4985 void ARMBaseInstrInfo::setExecutionDomain(MachineInstr &MI,
5193 unsigned ARMBaseInstrInfo::getPartialRegUpdateClearance(
5254 void ARMBaseInstrInfo::breakPartialRegDependency(
5288 bool ARMBaseInstrInfo::hasNOP() const {
5292 bool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const {
5306 bool ARMBaseInstrInfo::getRegSequenceLikeInputs(
5333 bool ARMBaseInstrInfo::getExtractSubregLikeInputs(
5356 bool ARMBaseInstrInfo::getInsertSubregLikeInputs(
5382 ARMBaseInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
5388 ARMBaseInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
5397 ARMBaseInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const {
5410 Optional<RegImmPair> ARMBaseInstrInfo::isAddImmediate(const MachineInstr &MI,
5644 ARMBaseInstrInfo::findRegisterToSaveLRTo(const outliner::Candidate &C) const {
5665 outliner::OutlinedFunction ARMBaseInstrInfo::getOutliningCandidateInfo(
5785 bool ARMBaseInstrInfo::isFunctionSafeToOutlineFrom(
5808 bool ARMBaseInstrInfo::isMBBSafeToOutlineFrom(MachineBasicBlock &MBB,
5851 ARMBaseInstrInfo::getOutliningType(MachineBasicBlock::iterator &MIT,
5964 void ARMBaseInstrInfo::buildOutlinedFrame(
5996 MachineBasicBlock::iterator ARMBaseInstrInfo::insertOutlinedCall(