Lines Matching refs:Add
68 // Returns true if result of \p Add is not used before \p Ldst
69 bool noUseOfAddBeforeLoadOrStore(const MachineInstr *Add,
80 // Check if instructions \p Ldst and \p Add can be moved to become adjacent
84 MachineInstr *canJoinInstructions(MachineInstr *Ldst, MachineInstr *Add,
182 bool ARCOptAddrMode::noUseOfAddBeforeLoadOrStore(const MachineInstr *Add,
184 Register R = Add->getOperand(0).getReg();
220 for (auto &Add : MRI->use_nodbg_instructions(B)) {
222 if (!isAddConstantOp(Add, Incr))
228 MachineInstr *MoveTo = canJoinInstructions(&Ldst, &Add, &Uses);
233 if (!canFixPastUses(Uses, Add.getOperand(2), B))
236 LLVM_DEBUG(MachineInstr *First = &Ldst; MachineInstr *Last = &Add;
244 if (MoveTo == &Add) {
246 Add.getParent()->insertAfter(Add.getIterator(), &Ldst);
248 if (Result == &Add)
255 unsigned NewBaseReg = Add.getOperand(0).getReg();
256 changeToAddrMode(Ldst, NewOpcode, NewBaseReg, Add.getOperand(2));
257 Add.eraseFromParent();
265 ARCOptAddrMode::canJoinInstructions(MachineInstr *Ldst, MachineInstr *Add,
267 assert(Ldst && Add && "NULL instruction passed");
269 MachineInstr *First = Add;
271 if (MDT->dominates(Ldst, Add))
273 else if (!MDT->dominates(Add, Ldst))
297 if (Add->getOperand(0).getReg() == StReg || BaseReg == StReg) {
298 LLVM_DEBUG(dbgs() << "[canJoinInstructions] Store uses result of Add\n");
306 if (&MI == Ldst || &MI == Add)
308 if (&MI != Add && MDT->dominates(Ldst, &MI))
312 if (MDT->dominates(Add, &MI))
318 if (First == Add) {
325 LLVM_DEBUG(dbgs() << "[canJoinInstructions] Can sink Add down to Ldst\n");
326 } else if (canHoistLoadStoreTo(Ldst, Add)) {
328 LLVM_DEBUG(dbgs() << "[canJoinInstructions] Can hoist Ldst to Add\n");
335 LLVM_DEBUG(dbgs() << "[canJoinInstructions] Can hoist Add to Ldst\n");