Lines Matching defs:AMDGPU
1 //===- AMDGPUBaseInfo.cpp - AMDGPU Base encoding information --------------===//
10 #include "AMDGPU.h"
104 namespace AMDGPU {
430 STI->getFeatureBits().test(AMDGPU::FeatureXNACK));
753 IdSymbolic[Id] && (Id != ID_XNACK_MASK || !AMDGPU::isGFX10_BEncoding(STI));
944 return STI.getFeatureBits()[AMDGPU::FeatureXNACK];
948 return STI.getFeatureBits()[AMDGPU::FeatureSRAMECC];
952 return STI.getFeatureBits()[AMDGPU::FeatureMIMG_R128] && !STI.getFeatureBits()[AMDGPU::FeatureR128A16];
956 return STI.getFeatureBits()[AMDGPU::FeatureGFX10A16];
960 return STI.getFeatureBits()[AMDGPU::FeatureG16];
964 return !STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem];
968 return STI.getFeatureBits()[AMDGPU::FeatureSouthernIslands];
972 return STI.getFeatureBits()[AMDGPU::FeatureSeaIslands];
976 return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
980 return STI.getFeatureBits()[AMDGPU::FeatureGFX9];
984 return STI.getFeatureBits()[AMDGPU::FeatureGFX10];
988 return STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding];
992 return STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding];
996 return STI.getFeatureBits()[AMDGPU::FeatureGFX10_3Insts];
1000 const MCRegisterClass SGPRClass = TRI->getRegClass(AMDGPU::SReg_32RegClassID);
1001 const unsigned FirstSubReg = TRI->getSubReg(Reg, AMDGPU::sub0);
1003 Reg == AMDGPU::SCC;
1014 using namespace AMDGPU; \
1084 return OpType >= AMDGPU::OPERAND_SRC_FIRST &&
1085 OpType <= AMDGPU::OPERAND_SRC_LAST;
1092 case AMDGPU::OPERAND_REG_IMM_FP32:
1093 case AMDGPU::OPERAND_REG_IMM_FP64:
1094 case AMDGPU::OPERAND_REG_IMM_FP16:
1095 case AMDGPU::OPERAND_REG_IMM_V2FP16:
1096 case AMDGPU::OPERAND_REG_IMM_V2INT16:
1097 case AMDGPU::OPERAND_REG_INLINE_C_FP32:
1098 case AMDGPU::OPERAND_REG_INLINE_C_FP64:
1099 case AMDGPU::OPERAND_REG_INLINE_C_FP16:
1100 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
1101 case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
1102 case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
1103 case AMDGPU::OPERAND_REG_INLINE_AC_FP16:
1104 case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:
1105 case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:
1115 return OpType >= AMDGPU::OPERAND_REG_INLINE_C_FIRST &&
1116 OpType <= AMDGPU::OPERAND_REG_INLINE_C_LAST;
1123 case AMDGPU::VGPR_LO16RegClassID:
1124 case AMDGPU::VGPR_HI16RegClassID:
1125 case AMDGPU::SGPR_LO16RegClassID:
1126 case AMDGPU::AGPR_LO16RegClassID:
1128 case AMDGPU::SGPR_32RegClassID:
1129 case AMDGPU::VGPR_32RegClassID:
1130 case AMDGPU::VRegOrLds_32RegClassID:
1131 case AMDGPU::AGPR_32RegClassID:
1132 case AMDGPU::VS_32RegClassID:
1133 case AMDGPU::AV_32RegClassID:
1134 case AMDGPU::SReg_32RegClassID:
1135 case AMDGPU::SReg_32_XM0RegClassID:
1136 case AMDGPU::SRegOrLds_32RegClassID:
1138 case AMDGPU::SGPR_64RegClassID:
1139 case AMDGPU::VS_64RegClassID:
1140 case AMDGPU::AV_64RegClassID:
1141 case AMDGPU::SReg_64RegClassID:
1142 case AMDGPU::VReg_64RegClassID:
1143 case AMDGPU::AReg_64RegClassID:
1144 case AMDGPU::SReg_64_XEXECRegClassID:
1146 case AMDGPU::SGPR_96RegClassID:
1147 case AMDGPU::SReg_96RegClassID:
1148 case AMDGPU::VReg_96RegClassID:
1149 case AMDGPU::AReg_96RegClassID:
1151 case AMDGPU::SGPR_128RegClassID:
1152 case AMDGPU::SReg_128RegClassID:
1153 case AMDGPU::VReg_128RegClassID:
1154 case AMDGPU::AReg_128RegClassID:
1156 case AMDGPU::SGPR_160RegClassID:
1157 case AMDGPU::SReg_160RegClassID:
1158 case AMDGPU::VReg_160RegClassID:
1159 case AMDGPU::AReg_160RegClassID:
1161 case AMDGPU::SGPR_192RegClassID:
1162 case AMDGPU::SReg_192RegClassID:
1163 case AMDGPU::VReg_192RegClassID:
1164 case AMDGPU::AReg_192RegClassID:
1166 case AMDGPU::SGPR_256RegClassID:
1167 case AMDGPU::SReg_256RegClassID:
1168 case AMDGPU::VReg_256RegClassID:
1169 case AMDGPU::AReg_256RegClassID:
1171 case AMDGPU::SGPR_512RegClassID:
1172 case AMDGPU::SReg_512RegClassID:
1173 case AMDGPU::VReg_512RegClassID:
1174 case AMDGPU::AReg_512RegClassID:
1176 case AMDGPU::SGPR_1024RegClassID:
1177 case AMDGPU::SReg_1024RegClassID:
1178 case AMDGPU::VReg_1024RegClassID:
1179 case AMDGPU::AReg_1024RegClassID:
1264 return AMDGPU::isInlinableLiteral16(Trunc, HasInv2Pi);
1267 return AMDGPU::isInlinableLiteral16(Literal >> 16, HasInv2Pi);
1498 } // namespace AMDGPU