Lines Matching defs:MIB
820 auto MIB = spillVGPRtoAGPR(ST, MI, Index, i, SubReg, IsKill);
822 if (!MIB.getInstr()) {
836 MIB = BuildMI(*MBB, MI, DL, Desc)
841 MIB.addImm(0);
843 MIB.addReg(SOffset, SOffsetRegState);
845 MIB.addImm(Offset)
854 MIB = BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_ACCVGPR_WRITE_B32),
860 MIB.addReg(ValueReg, RegState::Implicit | SrcDstRegState);
1133 auto MIB =
1139 MIB.addReg(SuperReg, RegState::ImplicitDefine);
1162 auto MIB =
1168 MIB.addReg(SuperReg, RegState::ImplicitDefine);
1340 if (auto MIB = TII->getAddNoCarry(*MBB, MI, DL, ResultReg, *RS)) {
1344 BuildMI(*MBB, *MIB, DL, TII->get(AMDGPU::V_LSHRREV_B32_e64),
1349 const bool IsVOP2 = MIB->getOpcode() == AMDGPU::V_ADD_U32_e32;
1354 MIB.addImm(Offset);
1355 MIB.addReg(ScaledReg, RegState::Kill);
1357 MIB.addImm(0); // clamp bit
1359 assert(MIB->getOpcode() == AMDGPU::V_ADD_I32_e64 &&
1365 ConstOffsetReg = getSubReg(MIB.getReg(1), AMDGPU::sub0);
1367 ConstOffsetReg = MIB.getReg(1);
1369 BuildMI(*MBB, *MIB, DL, TII->get(AMDGPU::S_MOV_B32), ConstOffsetReg)
1371 MIB.addReg(ConstOffsetReg, RegState::Kill);
1372 MIB.addReg(ScaledReg, RegState::Kill);
1373 MIB.addImm(0); // clamp bit