Lines Matching refs:TII
148 void processBlockPhase1(MachineBasicBlock &MBB, const SIInstrInfo *TII);
150 void processBlockPhase2(MachineBasicBlock &MBB, const SIInstrInfo *TII);
152 void processBlockPhase3(MachineBasicBlock &MBB, const SIInstrInfo *TII);
154 Status getInstructionMode(MachineInstr &MI, const SIInstrInfo *TII);
157 const SIInstrInfo *TII, Status InstrMode);
175 const SIInstrInfo *TII) {
176 if (TII->usesFPDPRounding(MI)) {
197 const SIInstrInfo *TII, Status InstrMode) {
202 BuildMI(MBB, MI, 0, TII->get(AMDGPU::S_SETREG_IMM32_B32))
233 const SIInstrInfo *TII) {
244 Status InstrMode = getInstructionMode(MI, TII);
250 unsigned Dst = TII->getNamedOperand(MI, AMDGPU::OpName::simm16)->getImm();
264 insertSetreg(MBB, InsertionPoint, TII, IPChange.delta(NewInfo->Change));
271 unsigned Val = TII->getNamedOperand(MI, AMDGPU::OpName::imm)->getImm();
297 insertSetreg(MBB, InsertionPoint, TII,
321 insertSetreg(MBB, InsertionPoint, TII, IPChange.delta(NewInfo->Change));
332 const SIInstrInfo *TII) {
400 const SIInstrInfo *TII) {
406 insertSetreg(MBB, BlockInfo[ThisBlock]->FirstInsertionPoint, TII, Delta);
408 insertSetreg(MBB, &MBB.instr_front(), TII, Delta);
415 const SIInstrInfo *TII = ST.getInstrInfo();
422 processBlockPhase1(BB, TII);
430 processBlockPhase2(*Phase2List.front(), TII);
437 processBlockPhase3(BB, TII);