Lines Matching refs:Base
198 BaseRegisters Base;
263 void processBaseWithConstOffset(const MachineOperand &Base, MemAddress &Addr) const;
1650 assert((TRI->getRegSizeInBits(Addr.Base.LoReg, *MRI) == 32 ||
1651 Addr.Base.LoSubReg) &&
1652 "Expected 32-bit Base-Register-Low!!");
1654 assert((TRI->getRegSizeInBits(Addr.Base.HiReg, *MRI) == 32 ||
1655 Addr.Base.HiSubReg) &&
1656 "Expected 32-bit Base-Register-Hi!!");
1658 LLVM_DEBUG(dbgs() << " Re-Computed Anchor-Base:\n");
1672 .addReg(Addr.Base.LoReg, 0, Addr.Base.LoSubReg)
1681 .addReg(Addr.Base.HiReg, 0, Addr.Base.HiSubReg)
1705 auto Base = TII->getNamedOperand(MI, AMDGPU::OpName::vaddr);
1706 Base->setReg(NewBase);
1707 Base->setIsKill(false);
1727 // Analyze Base and extracts:
1735 // %Base:vreg_64 =
1737 void SILoadStoreOptimizer::processBaseWithConstOffset(const MachineOperand &Base,
1739 if (!Base.isReg())
1742 MachineInstr *Def = MRI->getUniqueVRegDef(Base.getReg());
1783 Addr.Base.LoReg = BaseLo.getReg();
1784 Addr.Base.HiReg = BaseHi.getReg();
1785 Addr.Base.LoSubReg = BaseLo.getSubReg();
1786 Addr.Base.HiSubReg = BaseHi.getSubReg();
1816 MachineOperand &Base = *TII->getNamedOperand(MI, AMDGPU::OpName::vaddr);
1819 processBaseWithConstOffset(Base, MAddr);
1830 LLVM_DEBUG(dbgs() << " BASE: {" << MAddr.Base.HiReg << ", "
1831 << MAddr.Base.LoReg << "} Offset: " << MAddr.Offset << "\n\n";);
1887 if (MAddrNext.Base.LoReg != MAddr.Base.LoReg ||
1888 MAddrNext.Base.HiReg != MAddr.Base.HiReg ||
1889 MAddrNext.Base.LoSubReg != MAddr.Base.LoSubReg ||
1890 MAddrNext.Base.HiSubReg != MAddr.Base.HiSubReg)
1915 Register Base = computeBase(MI, AnchorAddr);
1917 updateBaseAndOffset(MI, Base, MAddr.Offset - AnchorAddr.Offset);
1928 updateBaseAndOffset(*P.first, Base, P.second - AnchorAddr.Offset);
1949 // Base address not found, so add a new list.