Lines Matching refs:getRegClass
868 const TargetRegisterClass *RegClass = MRI.getRegClass(DestReg);
934 RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
935 assert(MRI.getRegClass(DstReg) == &AMDGPU::VGPR_32RegClass &&
2339 const TargetRegisterClass *RC = MRI.getRegClass(TrueReg);
2340 assert(MRI.getRegClass(FalseReg) == RC);
2353 const TargetRegisterClass *RC = MRI.getRegClass(TrueReg);
2354 assert(MRI.getRegClass(FalseReg) == RC);
2381 const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg);
2624 if (!Src1->isReg() || RI.isSGPRClass(MRI->getRegClass(Src1->getReg())))
2627 if (!Src2->isReg() || RI.isSGPRClass(MRI->getRegClass(Src2->getReg())))
2694 RI.isSGPRClass(MRI->getRegClass(Src0->getReg())))))
2710 RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))))
3424 return RI.isSGPRClass(MRI.getRegClass(MO.getReg()));
3606 const TargetRegisterClass *RC = RI.getRegClass(RegClass);
4154 return MRI.getRegClass(Reg);
4159 return RI.getRegClass(RCID);
4170 const TargetRegisterClass *RC = RI.getRegClass(RCID);
4259 ? MRI.getRegClass(Reg)
4262 const TargetRegisterClass *DRC = RI.getRegClass(OpInfo.RegClass);
4295 OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;
4478 if (Src1.isReg() && !RI.isSGPRClass(MRI.getRegClass(Src1.getReg()))) {
4484 if (Src2.isReg() && !RI.isSGPRClass(MRI.getRegClass(Src2.getReg()))) {
4524 if (RI.hasAGPRs(MRI.getRegClass(MO.getReg())) &&
4530 if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
4551 const TargetRegisterClass *VRC = MRI.getRegClass(SrcReg);
4599 if (SBase && !RI.isSGPRClass(MRI.getRegClass(SBase->getReg()))) {
4604 if (SOff && !RI.isSGPRClass(MRI.getRegClass(SOff->getReg()))) {
4670 const auto *BoolXExecRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
4751 const auto *BoolXExecRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
4884 MRI.getRegClass(MI.getOperand(i).getReg());
4945 const TargetRegisterClass *OpRC = MRI.getRegClass(Op.getReg());
4963 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
4964 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);
4976 if (Src.isReg() && RI.hasVectorRegisters(MRI.getRegClass(Src.getReg())))
4990 if (SRsrc && !RI.isSGPRClass(MRI.getRegClass(SRsrc->getReg()))) {
4996 if (SSamp && !RI.isSGPRClass(MRI.getRegClass(SSamp->getReg()))) {
5010 if (RI.getCommonSubClass(MRI.getRegClass(Rsrc->getReg()),
5011 RI.getRegClass(RsrcRC))) {
5040 const auto *BoolXExecRC = RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
5344 const auto *CarryRC = RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
5356 MRI.getRegClass(Inst.getOperand(0).getReg())));
5382 RI.getEquivalentVGPRClass(MRI.getRegClass(Dest0.getReg()));
5671 RI.isSGPRClass(MRI.getRegClass(Src0.getReg()));
5673 RI.isSGPRClass(MRI.getRegClass(Src1.getReg()));
5780 MRI.getRegClass(Src0.getReg()) :
5788 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
5827 const auto *CarryRC = RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
5842 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0.getReg());
5843 const TargetRegisterClass *Src1RC = MRI.getRegClass(Src1.getReg());
5907 MRI.getRegClass(Src0.getReg()) :
5912 MRI.getRegClass(Src1.getReg()) :
5926 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
5969 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
6011 MRI.getRegClass(Src.getReg()) :
6334 const TargetRegisterClass *OpRC = RI.getRegClass(Desc.OpInfo[Idx].RegClass);
6341 const TargetRegisterClass *RegRC = MRI.getRegClass(Reg);
6789 return RI.getRegClass(RCID)->hasSubClassEq(&AMDGPU::SGPR_128RegClass);
7131 const TargetRegisterClass *RC = MRI.getRegClass(VirtReg);