Lines Matching refs:OpInfo
3199 const MCOperandInfo &OpInfo) const {
3204 return !isInlineConstant(MO, OpInfo);
3234 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpNo];
3238 if (OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE)
3241 if (OpInfo.RegClass < 0)
3247 if (MO.isImm() && isInlineConstant(MO, OpInfo)) {
3252 return RI.opCanUseInlineConstant(OpInfo.OperandType);
3255 if (!RI.opCanUseLiteralConstant(OpInfo.OperandType))
3410 const MCOperandInfo &OpInfo) const {
3412 //if (isLiteralConstantLike(MO, OpInfo))
3415 return !isInlineConstant(MO, OpInfo);
3555 int RegClass = Desc.OpInfo[i].RegClass;
3557 switch (Desc.OpInfo[i].OperandType) {
3765 if (usesConstantBus(MRI, MO, MI.getDesc().OpInfo[OpIdx])) {
3813 if (usesConstantBus(MRI, MO, MI.getDesc().OpInfo[OpIdx])) {
3848 !isInlineConstant(Src0, Desc.OpInfo[Src0Idx].OperandType))
3851 !isInlineConstant(Src1, Desc.OpInfo[Src1Idx].OperandType))
4150 Desc.OpInfo[OpNo].RegClass == -1) {
4158 unsigned RCID = Desc.OpInfo[OpNo].RegClass;
4169 unsigned RCID = get(MI.getOpcode()).OpInfo[OpIdx].RegClass;
4252 const MCOperandInfo &OpInfo,
4262 const TargetRegisterClass *DRC = RI.getRegClass(OpInfo.RegClass);
4277 const MCOperandInfo &OpInfo,
4280 return isLegalRegOperand(MRI, OpInfo, MO);
4292 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx];
4295 OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;
4301 if (isVALU(MI) && usesConstantBus(MRI, *MO, OpInfo)) {
4302 if (isVOP3(MI) && isLiteralConstantLike(*MO, OpInfo) && !VOP3LiteralLimit--)
4316 usesConstantBus(MRI, Op, InstDesc.OpInfo[i])) {
4321 } else if (InstDesc.OpInfo[i].OperandType == AMDGPU::OPERAND_KIMM32) {
4325 isLiteralConstantLike(Op, InstDesc.OpInfo[i])) {
4336 return isLegalRegOperand(MRI, OpInfo, *MO);
4366 isLiteralConstantLike(Src0, InstrDesc.OpInfo[Src0Idx])))
4399 if (isLegalRegOperand(MRI, InstrDesc.OpInfo[Src1Idx], Src1))
4430 !isLegalRegOperand(MRI, InstrDesc.OpInfo[Src1Idx], Src0)) {
4509 if (!isLiteralConstantLike(MO, get(Opc).OpInfo[Idx]))
5009 unsigned RsrcRC = get(MI.getOpcode()).OpInfo[RsrcIdx].RegClass;
6334 const TargetRegisterClass *OpRC = RI.getRegClass(Desc.OpInfo[Idx].RegClass);
6516 if (isLiteralConstantLike(MI.getOperand(Src0Idx), Desc.OpInfo[Src0Idx]))
6523 if (isLiteralConstantLike(MI.getOperand(Src1Idx), Desc.OpInfo[Src1Idx]))
6530 if (isLiteralConstantLike(MI.getOperand(Src2Idx), Desc.OpInfo[Src2Idx]))
6788 const auto RCID = MI.getDesc().OpInfo[Idx].RegClass;